F. Ribeiro, A. Rettberg, C. Pereira, Charles Steinmetz, M. S. Soares
{"title":"Model-Based Design Methodology for Early Evaluation of Real-time and Embedded Constraints","authors":"F. Ribeiro, A. Rettberg, C. Pereira, Charles Steinmetz, M. S. Soares","doi":"10.1109/INDIN.2018.8471976","DOIUrl":null,"url":null,"abstract":"When developing Real-Time and Embedded Systems (RTES), different types of constraints should be considered in specification, modeling, architectural design and system implementation. In most cases, these constraints describe timing, precedence or resource restriction. Correct description and evaluation of these complex information along of RTES design are directly related to their reliability, safety and quality. In this research, a methodology to describe real-time and embedded information in requirements, functional, logical and technical viewpoints is briefly presented, as well as an approach to analyze the annotated constraints. MARTE constraints have been consistently applied in designing models and implemented at lower abstraction models. Here, pseudo automated generation of timing, precedence and resources constraints is performed from the graphical models to the final source code models. Therefore, the proposed approach has a great value to RTES design once it has traced constraints along of the architectural design and it also presents a manner to check if constraints are being reached in accordance with early design description.","PeriodicalId":6467,"journal":{"name":"2018 IEEE 16th International Conference on Industrial Informatics (INDIN)","volume":"172 1","pages":"875-881"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 16th International Conference on Industrial Informatics (INDIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INDIN.2018.8471976","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
When developing Real-Time and Embedded Systems (RTES), different types of constraints should be considered in specification, modeling, architectural design and system implementation. In most cases, these constraints describe timing, precedence or resource restriction. Correct description and evaluation of these complex information along of RTES design are directly related to their reliability, safety and quality. In this research, a methodology to describe real-time and embedded information in requirements, functional, logical and technical viewpoints is briefly presented, as well as an approach to analyze the annotated constraints. MARTE constraints have been consistently applied in designing models and implemented at lower abstraction models. Here, pseudo automated generation of timing, precedence and resources constraints is performed from the graphical models to the final source code models. Therefore, the proposed approach has a great value to RTES design once it has traced constraints along of the architectural design and it also presents a manner to check if constraints are being reached in accordance with early design description.