A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time

Tejasvi Anand, Mrunmay Talegaonkar, A. Elshazly, B. Young, P. Hanumolu
{"title":"A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time","authors":"Tejasvi Anand, Mrunmay Talegaonkar, A. Elshazly, B. Young, P. Hanumolu","doi":"10.1109/ISSCC.2013.6487724","DOIUrl":null,"url":null,"abstract":"Modern mobile platforms utilize power cycling to lower power dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on time [1-2]. Techniques such as dynamic phase-error compensation [3], edge-missing compensation [4], and hybrid PLLs [5] improve the phase acquisition time to at best few hundred reference cycles. However, such improvements are inadequate to make best use of power-cycling. Multiplying injection-locked oscillators (MILO) are shown to lock faster than PLLs, but suffer from conflicting requirements on injection strength to simultaneously achieve low jitter and fast locking. Increasing the injection strength extends lock range and reduces locking time, but severely degrades the deterministic jitter performance [6]. In view of these drawbacks, we propose a highly digital clock multiplier that seeks to achieve low jitter, fast locking, and near-zero off-state power. By using a highly scalable digital architecture with accurate frequency presetting and instantaneous phase acquisition, the prototype 8×/16× clock multiplier achieves 10ns (3 reference cycles) power-on time, 2psrms long-term absolute jitter, less than 25μW off-state power, 12pJ energy overhead for on/off transition, and 2.2mW on-state power at 2.5GHz output frequency.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2013.6487724","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

Modern mobile platforms utilize power cycling to lower power dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on time [1-2]. Techniques such as dynamic phase-error compensation [3], edge-missing compensation [4], and hybrid PLLs [5] improve the phase acquisition time to at best few hundred reference cycles. However, such improvements are inadequate to make best use of power-cycling. Multiplying injection-locked oscillators (MILO) are shown to lock faster than PLLs, but suffer from conflicting requirements on injection strength to simultaneously achieve low jitter and fast locking. Increasing the injection strength extends lock range and reduces locking time, but severely degrades the deterministic jitter performance [6]. In view of these drawbacks, we propose a highly digital clock multiplier that seeks to achieve low jitter, fast locking, and near-zero off-state power. By using a highly scalable digital architecture with accurate frequency presetting and instantaneous phase acquisition, the prototype 8×/16× clock multiplier achieves 10ns (3 reference cycles) power-on time, 2psrms long-term absolute jitter, less than 25μW off-state power, 12pJ energy overhead for on/off transition, and 2.2mW on-state power at 2.5GHz output frequency.
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2.5GHz 2.2mW/25µW开/关状态功率2psms -长抖动数字时钟乘法器,通电时间为3个参考周期
现代移动平台利用功率循环来降低功耗并延长电池寿命。通过关闭不使用的电路,功率循环提供了一种可行的方法,使功耗与工作负载成比例,从而实现能量比例运行。这种方法的有效性取决于开/关时间、非状态功耗和由于功率循环引起的能量开销。理想情况下,电路必须在零时间内打开/关闭,不消耗断开状态功率,并且在通-关和关-通转换期间产生最小的能量开销。使用锁相环(pll)实现的传统时钟乘法器由于锁定时间长,在实现这些性能目标方面存在最大的瓶颈。即使锁相环是锁频的,缓慢的相位采集过程限制了上电时间[1-2]。动态相位误差补偿[3]、边缘缺失补偿[4]和混合锁相环[5]等技术将相位采集时间最多提高到几百个参考周期。然而,这些改进不足以充分利用电力循环。倍增注入锁定振荡器(MILO)的锁定速度比锁相环快,但同时实现低抖动和快速锁定的注入强度存在冲突要求。增加注入强度可以扩大锁定范围,缩短锁定时间,但会严重降低确定性抖动性能[6]。鉴于这些缺点,我们提出了一种高数字时钟乘法器,旨在实现低抖动,快速锁定和接近零的非状态功率。通过采用高度可扩展的数字架构,精确的频率预置和瞬时相位采集,原型8×/16×时钟乘法器在2.5GHz输出频率下实现了10ns(3个参考周期)的上电时间、2psrms的长期绝对抖动、小于25μW的关断功率、12pJ的开关转换能量开销和2.2mW的导通功率。
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