{"title":"Dynamic Weight Ranking algorithm using R-F score for Efficient Caching","authors":"Debabrata Swain, Shreerag Marar, Nikhil Motwani, Vivek Hiwarkar, Puran Singh","doi":"10.1109/ICACAT.2018.8933642","DOIUrl":null,"url":null,"abstract":"There is a huge gap in the performance of the processor and the main memory. The speed of processor is much greater as compared to that of the main memory. The concept of paging has significantly increased the number of main memory accesses. In order to reduce the main memory access, a special hardware called the cache memory had been introduced. The cache memory bridges the performance gap between the main memory and the processor. This paper proposes a more efficient way to evaluate the weight factor thereby improving the results evaluated using CWRP [1]. The proposed work is easy to implement and provides better results compared to Least-Recently-Used (LRU), Clock with Adaptive Replacement (CAR) and First-In-First-Out (FIFO).","PeriodicalId":6575,"journal":{"name":"2018 International Conference on Advanced Computation and Telecommunication (ICACAT)","volume":"113 1","pages":"1-7"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Advanced Computation and Telecommunication (ICACAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICACAT.2018.8933642","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
There is a huge gap in the performance of the processor and the main memory. The speed of processor is much greater as compared to that of the main memory. The concept of paging has significantly increased the number of main memory accesses. In order to reduce the main memory access, a special hardware called the cache memory had been introduced. The cache memory bridges the performance gap between the main memory and the processor. This paper proposes a more efficient way to evaluate the weight factor thereby improving the results evaluated using CWRP [1]. The proposed work is easy to implement and provides better results compared to Least-Recently-Used (LRU), Clock with Adaptive Replacement (CAR) and First-In-First-Out (FIFO).