Jiangjiang Gu, Xinwei Wang, J. Shao, A. Neal, M. Manfra, Roy G. Gordon, P. D. Ye
{"title":"III–V 4D transistors","authors":"Jiangjiang Gu, Xinwei Wang, J. Shao, A. Neal, M. Manfra, Roy G. Gordon, P. D. Ye","doi":"10.1109/DRC.2012.6256964","DOIUrl":null,"url":null,"abstract":"We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/μm and high transconductance of 0.85mS/μm. The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"50 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"70th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2012.6256964","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/μm and high transconductance of 0.85mS/μm. The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.
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