{"title":"A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique","authors":"Alessandro Garghetti, A. Lacaita, S. Levantino","doi":"10.1109/ISCAS.2018.8350910","DOIUrl":null,"url":null,"abstract":"A novel low-power and wide-locking-range divide-by-three injection-locked frequency divider with single inductor is presented in this paper. The classical topology with divide-by-two locking scheme is improved via the introduction of an extra tail-injection driven by the central node of the floating-source direct injector. This new concept is applied to the design of a 15GHz divider-by-three in a standard 65-nm LP CMOS technology, which reaches, in post-layout simulations at 100° C temperature, a 23.6% locking range at an input power of 0dBm and DC power consumption of 1.56mW. The divider figure of merit together with the compact size of only 0.09mm2 are best in class for injection-locking dividers with single inductor and same input power. The figure of merit is also very close to the values reached by the best injection-locking dividers-by-three, that, however, use more inductors.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"23 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2018.8350910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A novel low-power and wide-locking-range divide-by-three injection-locked frequency divider with single inductor is presented in this paper. The classical topology with divide-by-two locking scheme is improved via the introduction of an extra tail-injection driven by the central node of the floating-source direct injector. This new concept is applied to the design of a 15GHz divider-by-three in a standard 65-nm LP CMOS technology, which reaches, in post-layout simulations at 100° C temperature, a 23.6% locking range at an input power of 0dBm and DC power consumption of 1.56mW. The divider figure of merit together with the compact size of only 0.09mm2 are best in class for injection-locking dividers with single inductor and same input power. The figure of merit is also very close to the values reached by the best injection-locking dividers-by-three, that, however, use more inductors.