Pub Date : 2018-05-30DOI: 10.1109/ISCAS.2018.8351091
Mohammad Mehdi Moayer, Jarno Salomaa, M. Pulkkinen, K. Halonen
This paper presents an ultra-low power, wide-dynamic-range interface circuit for capacitive and resistive sensors. It is implemented as a switched-capacitor circuit using tunable capacitors to achieve high configurability. The circuit was fabricated using a 0.18μm CMOS technology. Measured results show that the circuit is able to interface various sensors within the overall capacitance range of 0.6–550pF and resistance range of 3.7kΩ–5.1MΩ, while consuming only 0.39–3.56μW, from a 1.2V supply.
{"title":"Ultra-Low Power Wide-Dynamic-Range Universal Interface for Capacitive and Resistive Sensors","authors":"Mohammad Mehdi Moayer, Jarno Salomaa, M. Pulkkinen, K. Halonen","doi":"10.1109/ISCAS.2018.8351091","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351091","url":null,"abstract":"This paper presents an ultra-low power, wide-dynamic-range interface circuit for capacitive and resistive sensors. It is implemented as a switched-capacitor circuit using tunable capacitors to achieve high configurability. The circuit was fabricated using a 0.18μm CMOS technology. Measured results show that the circuit is able to interface various sensors within the overall capacitance range of 0.6–550pF and resistance range of 3.7kΩ–5.1MΩ, while consuming only 0.39–3.56μW, from a 1.2V supply.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"211 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74480359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351685
G. Santoro, M. Casu, Valentino Peluso, A. Calimera, M. Alioto
Specialized computing engines are required to accelerate the execution of Deep Learning (DL) algorithms in an energy-efficient way. To adapt the processing throughput of these accelerators to the workload requirements while saving power, Dynamic Voltage and Frequency Scaling (DVFS) seems the natural solution. However, DL workloads need to frequently access the off-chip memory, which tends to make the performance of these accelerators memory-bound rather than computation-bound, hence reducing the effectiveness of DVFS. In this work we use a performance-power analytical model fitted on a parametrized implementation of a DL accelerator in a 28-nm FDSOI technology to explore a large design space and to obtain the Pareto points that maximize the effectiveness of DVFS in the sub-space of throughput and energy efficiency. In our model we consider the impact on performance and power of the off-chip memory using real data of a commercial low-power DRAM.
{"title":"Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS","authors":"G. Santoro, M. Casu, Valentino Peluso, A. Calimera, M. Alioto","doi":"10.1109/ISCAS.2018.8351685","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351685","url":null,"abstract":"Specialized computing engines are required to accelerate the execution of Deep Learning (DL) algorithms in an energy-efficient way. To adapt the processing throughput of these accelerators to the workload requirements while saving power, Dynamic Voltage and Frequency Scaling (DVFS) seems the natural solution. However, DL workloads need to frequently access the off-chip memory, which tends to make the performance of these accelerators memory-bound rather than computation-bound, hence reducing the effectiveness of DVFS. In this work we use a performance-power analytical model fitted on a parametrized implementation of a DL accelerator in a 28-nm FDSOI technology to explore a large design space and to obtain the Pareto points that maximize the effectiveness of DVFS in the sub-space of throughput and energy efficiency. In our model we consider the impact on performance and power of the off-chip memory using real data of a commercial low-power DRAM.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"176 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73444169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351395
Sheung Lu, Bathiya Senevirathna, M. Dandin, E. Smela, P. Abshire
Integrating CMOS sensor chips to allow for wet experimentation on lab-on-CMOS devices is a challenging task. In this paper we describe a chip packaging method that will allow for simple integration and handling of small integrated circuit (IC) chips. A chip is embedded in an epoxy handle wafer to allow for photolithographic processing. Electrical connections are provided by a sputter-deposited copper layer and an electroplated nickel layer. Passivation was performed using a second epoxy layer. The process was evaluated by packaging a capacitance sensor chip and performing live cell culture experiments with package cleaning and reuse. Results showed good structural reliability in three repeated experiments over five cumulative days, with no adverse effects on the viability of cells.
{"title":"System Integration of IC chips for Lab-on-CMOS Applications","authors":"Sheung Lu, Bathiya Senevirathna, M. Dandin, E. Smela, P. Abshire","doi":"10.1109/ISCAS.2018.8351395","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351395","url":null,"abstract":"Integrating CMOS sensor chips to allow for wet experimentation on lab-on-CMOS devices is a challenging task. In this paper we describe a chip packaging method that will allow for simple integration and handling of small integrated circuit (IC) chips. A chip is embedded in an epoxy handle wafer to allow for photolithographic processing. Electrical connections are provided by a sputter-deposited copper layer and an electroplated nickel layer. Passivation was performed using a second epoxy layer. The process was evaluated by packaging a capacitance sensor chip and performing live cell culture experiments with package cleaning and reuse. Results showed good structural reliability in three repeated experiments over five cumulative days, with no adverse effects on the viability of cells.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"39 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73933386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351813
Abdullah M. Zyarah, Nicholas Soures, D. Kudithipudi
In this paper, a memristor spiking neuron and synaptic trace circuits for efficient on device learning are presented. A key feature of these circuits is the use of memristors to emulate the membrane potential of spiking neurons, as opposed to the conventional use of a capacitor. The circuits are designed in IBM 65nm technology node and validated on a small-scale spiking neural network. It was observed that a 3×3 spiking neural network consumes 19.1 μW of power at 100 MHz.
{"title":"On-Device Learning in Memristor Spiking Neural Networks","authors":"Abdullah M. Zyarah, Nicholas Soures, D. Kudithipudi","doi":"10.1109/ISCAS.2018.8351813","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351813","url":null,"abstract":"In this paper, a memristor spiking neuron and synaptic trace circuits for efficient on device learning are presented. A key feature of these circuits is the use of memristors to emulate the membrane potential of spiking neurons, as opposed to the conventional use of a capacitor. The circuits are designed in IBM 65nm technology node and validated on a small-scale spiking neural network. It was observed that a 3×3 spiking neural network consumes 19.1 μW of power at 100 MHz.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"188 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73943157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351406
Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, C. Pham
Priority encoder (PE) is recognized as an indispensable component in the content-addressable memory. In this paper, two efficient architecture of 64-bit PE and 256-bit PE using 1D-array to 2D-array conversion (1D-to-2D) method are presented and implemented in a 65-nm Silicon-on-thin-buried-oxide (SOTB) CMOS process. The 1D-to-2D method is exploited because of its advantages in large-sized PE construction. The SOTB CMOS process is utilized because of its prominent advantages of low-power and high-performance configuration using back bias voltages. The measurement results at 1.2 V showed that a fabricated PE256 chip was fully operational at 45 MHz and consumed approximately 219 μW. Additionally, in sleep mode, the leakage power dropped as low as 0.34 μW at 0.6 V.
{"title":"A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS","authors":"Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, C. Pham","doi":"10.1109/ISCAS.2018.8351406","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351406","url":null,"abstract":"Priority encoder (PE) is recognized as an indispensable component in the content-addressable memory. In this paper, two efficient architecture of 64-bit PE and 256-bit PE using 1D-array to 2D-array conversion (1D-to-2D) method are presented and implemented in a 65-nm Silicon-on-thin-buried-oxide (SOTB) CMOS process. The 1D-to-2D method is exploited because of its advantages in large-sized PE construction. The SOTB CMOS process is utilized because of its prominent advantages of low-power and high-performance configuration using back bias voltages. The measurement results at 1.2 V showed that a fabricated PE256 chip was fully operational at 45 MHz and consumed approximately 219 μW. Additionally, in sleep mode, the leakage power dropped as low as 0.34 μW at 0.6 V.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"42 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77873448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351152
Suhwan Lim, J. Bae, Jai-Ho Eum, Sungtae Lee, Chul-Heung Kim, D. Kwon, Jong-Ho Lee
A gated Schottky diode is proposed for high-performance synapse devices and a means of designing a neural network using this device is described. The proposed gated Schottky diode operates in the saturation region with respect to the input voltage and is therefore immune to input noise and enables accurate vector-by-matrix multiplication. Moreover, by applying identical pulses to the bottom gate to store charges in a storage layer, the reverse saturation current increases almost linearly. Considering these special characteristics, we propose an architecture that uses a time-modulated input pulse and a learning rule based on a single conductance step. A three-layer perceptron network is trained using the conductance response of the synapse device and unidirectional weight-updating methods. In simulations using this network, the classification accuracy rate of MNIST training sets was found to be 94.50%. Compared to memristive devices, the improved linearity of the conductance response in our device is evidence of its higher accuracy.
{"title":"Hardware-based Neural Networks using a Gated Schottky Diode as a Synapse Device","authors":"Suhwan Lim, J. Bae, Jai-Ho Eum, Sungtae Lee, Chul-Heung Kim, D. Kwon, Jong-Ho Lee","doi":"10.1109/ISCAS.2018.8351152","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351152","url":null,"abstract":"A gated Schottky diode is proposed for high-performance synapse devices and a means of designing a neural network using this device is described. The proposed gated Schottky diode operates in the saturation region with respect to the input voltage and is therefore immune to input noise and enables accurate vector-by-matrix multiplication. Moreover, by applying identical pulses to the bottom gate to store charges in a storage layer, the reverse saturation current increases almost linearly. Considering these special characteristics, we propose an architecture that uses a time-modulated input pulse and a learning rule based on a single conductance step. A three-layer perceptron network is trained using the conductance response of the synapse device and unidirectional weight-updating methods. In simulations using this network, the classification accuracy rate of MNIST training sets was found to be 94.50%. Compared to memristive devices, the improved linearity of the conductance response in our device is evidence of its higher accuracy.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"23 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80505885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351592
M. Atienza, L. Kowalski, S. Gorreta, J. Pons-Nin, V. Jimenez, Manuel Domínguez Pumar
This paper presents a characterization method based on diffusive representation for a class of linear or nonlinear time-varying diffusive systems. The system variation with time may come as a result of the own actuation over the device or as a result of an external disturbance. Experimental results for both cases are presented. This method has been tested on a prototype of the REMS thermal wind anemometer for Mars atmosphere in which the time variation is induced by wind changes in a wind tunnel. The same method is also applied to model the nonlinear charge trapping dynamics of a contactless MEMS capacitor, in which the system variation with time comes from the nonlinear dependence on the applied voltages. In both cases, the obtained state-space models are able to reproduce and predict the behavior of the devices under arbitrary excitations.
{"title":"Model identification of Time-Varying Diffusive Systems","authors":"M. Atienza, L. Kowalski, S. Gorreta, J. Pons-Nin, V. Jimenez, Manuel Domínguez Pumar","doi":"10.1109/ISCAS.2018.8351592","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351592","url":null,"abstract":"This paper presents a characterization method based on diffusive representation for a class of linear or nonlinear time-varying diffusive systems. The system variation with time may come as a result of the own actuation over the device or as a result of an external disturbance. Experimental results for both cases are presented. This method has been tested on a prototype of the REMS thermal wind anemometer for Mars atmosphere in which the time variation is induced by wind changes in a wind tunnel. The same method is also applied to model the nonlinear charge trapping dynamics of a contactless MEMS capacitor, in which the system variation with time comes from the nonlinear dependence on the applied voltages. In both cases, the obtained state-space models are able to reproduce and predict the behavior of the devices under arbitrary excitations.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"12 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79009269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351558
Yuki Nishikawa, S. Izumi, Yuji Yano, H. Kawaguchi, M. Yoshimoto
This report describes a sampling rate reduction method for heart rate variability monitoring with a wearable device. This work was conducted to realize low-power measurement of biological signals necessary for heart rate variability (HRV) analysis. Continuous operation of the wearable device is an important factor for daily life monitoring. Therefore, the active time of the measuring circuit must be minimized. To reduce the required sampling rate, we propose a sampling error reduction method using interpolation and correlation of the heartbeat waveform. The proposed method is evaluated using measured electrocardiograms from five subjects. Evaluation results demonstrate that the sampling rate can be reduced to 32 Hz with 1 ms RMS error in heartbeat interval and 1.04% LF/HF degradation in HRV analysis.
{"title":"Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring","authors":"Yuki Nishikawa, S. Izumi, Yuji Yano, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ISCAS.2018.8351558","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351558","url":null,"abstract":"This report describes a sampling rate reduction method for heart rate variability monitoring with a wearable device. This work was conducted to realize low-power measurement of biological signals necessary for heart rate variability (HRV) analysis. Continuous operation of the wearable device is an important factor for daily life monitoring. Therefore, the active time of the measuring circuit must be minimized. To reduce the required sampling rate, we propose a sampling error reduction method using interpolation and correlation of the heartbeat waveform. The proposed method is evaluated using measured electrocardiograms from five subjects. Evaluation results demonstrate that the sampling rate can be reduced to 32 Hz with 1 ms RMS error in heartbeat interval and 1.04% LF/HF degradation in HRV analysis.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"55 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79020519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351777
P. Pereira, António C. Pinto, L. Oliveira, J. Fernandes
We present a generic model for Multiple Phase Ring Oscillators (MPRO) with 2n phases, and derive equations for frequency, phase and phase error under the simplifying approach of injecting the error in a single element. Extensive Monte Carlo simulations, at transistor level, for the four and eight phase circuits, are in accordance with these assumptions. These results are validated by two prototype integrated circuits, implemented in a 130 nm CMOS technology: The first prototype, which is a standalone four phases Ring Oscillator (RO), validates the theoretical analysis concerning the non-linear model main conclusions and, the second prototype, which is an eight phase RO, incorporated as a block of an ISM receiver, validates the generic model for CRO concept.
{"title":"Generic Model for Multi-Phase Ring Oscillators","authors":"P. Pereira, António C. Pinto, L. Oliveira, J. Fernandes","doi":"10.1109/ISCAS.2018.8351777","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351777","url":null,"abstract":"We present a generic model for Multiple Phase Ring Oscillators (MPRO) with 2n phases, and derive equations for frequency, phase and phase error under the simplifying approach of injecting the error in a single element. Extensive Monte Carlo simulations, at transistor level, for the four and eight phase circuits, are in accordance with these assumptions. These results are validated by two prototype integrated circuits, implemented in a 130 nm CMOS technology: The first prototype, which is a standalone four phases Ring Oscillator (RO), validates the theoretical analysis concerning the non-linear model main conclusions and, the second prototype, which is an eight phase RO, incorporated as a block of an ISM receiver, validates the generic model for CRO concept.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"36 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81930916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351789
G. Singh, Nagarjuna Nallam
This paper presents a CMOS inverter-like Class-D/E switching power amplifier (PA). The proposed amplifier operates in-between Class-E and Class-DE PAs. For proper operation of a Class-E PA, an RF choke (RFC) with large inductance value and high self-resonant frequency is necessary. A Class-DE PA does not require an RFC but requires a dead-time between OFF-ON transitions of the two switches. The proposed PA uses two complementary switches and requires neither an RFC nor a dead-time for its operation. For the same supply voltage and the load resistance, the voltage stress on each switching device in the proposed PA is less than the voltage stress in a Class-E PA. Design and simulation results of a prototype PA at 2.45 GHz with +20 dBm output power are presented.
{"title":"A CMOS Inverter-Like Class-D/E Power Amplifier with No RF-Choke and No Dead-Time Requirement","authors":"G. Singh, Nagarjuna Nallam","doi":"10.1109/ISCAS.2018.8351789","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351789","url":null,"abstract":"This paper presents a CMOS inverter-like Class-D/E switching power amplifier (PA). The proposed amplifier operates in-between Class-E and Class-DE PAs. For proper operation of a Class-E PA, an RF choke (RFC) with large inductance value and high self-resonant frequency is necessary. A Class-DE PA does not require an RFC but requires a dead-time between OFF-ON transitions of the two switches. The proposed PA uses two complementary switches and requires neither an RFC nor a dead-time for its operation. For the same supply voltage and the load resistance, the voltage stress on each switching device in the proposed PA is less than the voltage stress in a Class-E PA. Design and simulation results of a prototype PA at 2.45 GHz with +20 dBm output power are presented.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84546132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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