Design of an LDMOS Transistor Based on the 1 µm CMOS Process for High/Low Power Applications

Abstract

In this paper we investigate the performance of an integrated n-type laterally-diffused metal oxide semiconductor (nLDMOS) transistor, using 2D TCAD simulations. This work is based on the 1 µm CMOS technology node at CDTAs clean room. The nLDMOS process uses the necessary steps extracted from logic-integrated circuits fabrication flow, which yields to local oxidation of silicon (LOCOS), single reduced surface field (RESURF)-based nLDMOS, without needing any additional masks or steps. The resulting device has a 22 V breakdown voltage (BV) and 272 mm2 mΩ specific on-state resistance (RON). The analysis determined that the proposed device could be implemented in RF power amplifiers for wireless communications or automotive circuits as primary domains, provided experimental calibrations.