R. Sunil, K. SiddharthR., Nithin Y. B. Kumar, M. H. Vasantha
{"title":"An Asynchronous Analog to Digital Converter for Video Camera Applications","authors":"R. Sunil, K. SiddharthR., Nithin Y. B. Kumar, M. H. Vasantha","doi":"10.1109/ISVLSI.2019.00040","DOIUrl":null,"url":null,"abstract":"This paper proposes an asynchronous analog to digital converter (ADC) for wireless surveillance video camera applications. The proposed architecture is based on a nonuniform sampling, whose sampling instants depend on the input voltage amplitude. The proposed design has the power performance advantage, by using a power down comparator, for an input voltage close to the extreme values. Thus, the proposed architecture is suitable for the applications in which the input signal rarely assumes voltage values closer to the mid-range amplitude voltage. The design is simulated, at the transistor level, in a 180-nm CMOS technology. The results show that about 96.7% of the power can be saved in the best case (input voltage in the vicinity of extreme values) when compared to a conventional flash ADC.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"358 1","pages":"175-180"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2019.00040","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper proposes an asynchronous analog to digital converter (ADC) for wireless surveillance video camera applications. The proposed architecture is based on a nonuniform sampling, whose sampling instants depend on the input voltage amplitude. The proposed design has the power performance advantage, by using a power down comparator, for an input voltage close to the extreme values. Thus, the proposed architecture is suitable for the applications in which the input signal rarely assumes voltage values closer to the mid-range amplitude voltage. The design is simulated, at the transistor level, in a 180-nm CMOS technology. The results show that about 96.7% of the power can be saved in the best case (input voltage in the vicinity of extreme values) when compared to a conventional flash ADC.