{"title":"VLSI Implementation of Low Power FIR Filter using Variable Precision Two-Dimensional Pipeline Gating Multiplier","authors":"Satish Bojjawar, P. Benakop","doi":"10.37896/ymer21.08/08","DOIUrl":null,"url":null,"abstract":"The low-power FIR filter is required for many DSP applications. The crucial and powerhungry block in the filter is a multiplier. To implement the low power FIR filter a twodimensional variable precision fine-grain pipeline gating technique is introduced in the multiplier. The optimized multiplier is used to implement the transposed form-based FIR filter for the order N = 8 in ASIC design tools from Cadence in CMOS 45nm Technology. The designed FIR filter is compared with the existing multiplier-based FIR filters. The power-saving is achieved by the proposed filter is 22% without any degradation in the speed. The area penalty is 3% only due to the variable precision two-dimensional pipeline gating technique. Keywords: FIR filter, Fine grain pipeline, dynamic power, clock gating, low power multiplier, VLSI, and variable precision.","PeriodicalId":23848,"journal":{"name":"YMER Digital","volume":"40 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2022-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"YMER Digital","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.37896/ymer21.08/08","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The low-power FIR filter is required for many DSP applications. The crucial and powerhungry block in the filter is a multiplier. To implement the low power FIR filter a twodimensional variable precision fine-grain pipeline gating technique is introduced in the multiplier. The optimized multiplier is used to implement the transposed form-based FIR filter for the order N = 8 in ASIC design tools from Cadence in CMOS 45nm Technology. The designed FIR filter is compared with the existing multiplier-based FIR filters. The power-saving is achieved by the proposed filter is 22% without any degradation in the speed. The area penalty is 3% only due to the variable precision two-dimensional pipeline gating technique. Keywords: FIR filter, Fine grain pipeline, dynamic power, clock gating, low power multiplier, VLSI, and variable precision.