VLSI Implementation of Low Power FIR Filter using Variable Precision Two-Dimensional Pipeline Gating Multiplier

YMER Digital Pub Date : 2022-08-03 DOI:10.37896/ymer21.08/08
Satish Bojjawar, P. Benakop
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Abstract

The low-power FIR filter is required for many DSP applications. The crucial and powerhungry block in the filter is a multiplier. To implement the low power FIR filter a twodimensional variable precision fine-grain pipeline gating technique is introduced in the multiplier. The optimized multiplier is used to implement the transposed form-based FIR filter for the order N = 8 in ASIC design tools from Cadence in CMOS 45nm Technology. The designed FIR filter is compared with the existing multiplier-based FIR filters. The power-saving is achieved by the proposed filter is 22% without any degradation in the speed. The area penalty is 3% only due to the variable precision two-dimensional pipeline gating technique. Keywords: FIR filter, Fine grain pipeline, dynamic power, clock gating, low power multiplier, VLSI, and variable precision.
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可变精度二维管道门控乘法器低功耗FIR滤波器的VLSI实现
许多DSP应用都需要低功耗FIR滤波器。滤波器中关键且耗电的部分是乘法器。为了实现低功耗FIR滤波器,在乘法器中引入了二维变精度细颗粒管道门控技术。优化后的乘子用于在Cadence的CMOS 45nm技术ASIC设计工具中实现N = 8阶的基于转置形式的FIR滤波器。将所设计的FIR滤波器与现有的基于乘法器的FIR滤波器进行了比较。所提出的滤波器在不降低速度的情况下,节省了22%的功率。由于采用变精度二维管道浇注技术,面积损失仅为3%。关键词:FIR滤波器,细粒度管道,动态功率,时钟门控,低功率乘法器,VLSI,可变精度。
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