Fabrication and characterization of twin poly-Si thin film transistors EEPROM with nitride trapping layer

Abstract

This work demonstrates a novel twin poly-Si thin film transistor (TFT) EEPROM that utilizes oxide for gate dielectric and nitride for electron trapping layer (O/N twin poly-Si EEPROM). This EEPROM has superior reliability because its nitride for electron trapping layer provides a better program/erase efficiency and retention. For endurance and retention, the memory window can be maintained 2.5 V after 103 program and erase (P/E) cycles, and the memory window can be maintained 2.5 V after 104 s at 85 °C. This investigation explores its feasibility in future active matrix liquid crystal display (AMLCD) system-on-panel (SOP) and 3D stacked Flash memory applications.