Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection

Chien Chun-Hsien, Chien-Chou Chen, Wen-Liang Yeh, Wei Lin, Wu Cheng-Hui, Chen Fu-yang, Yi-Cheng Lin, Po-Chiang Wang, J. Li, Bo Cheng Lin, Yu-Hua Chen, T. Tseng
{"title":"Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection","authors":"Chien Chun-Hsien, Chien-Chou Chen, Wen-Liang Yeh, Wei Lin, Wu Cheng-Hui, Chen Fu-yang, Yi-Cheng Lin, Po-Chiang Wang, J. Li, Bo Cheng Lin, Yu-Hua Chen, T. Tseng","doi":"10.4071/2380-4505-2019.1.000216","DOIUrl":null,"url":null,"abstract":"\n In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (< 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"90 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4071/2380-4505-2019.1.000216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (< 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
研究了平板玻璃基板用于下一代互连的光可成像介质(PID)和非PID的工艺、制造和可靠性
1965年,英特尔的联合创始人戈登·e·摩尔(Gordon E. Moore)表示,芯片上的晶体管数量每18个月就会翻一番,他的理论被称为摩尔定律。50多年来,该定律一直是芯片设计的指导原则。集成电路代工厂的技术规模正在迅速扩大。例如,台积电宣布其5nm翅片场效应晶体管(FinFET)工艺技术针对移动和高性能计算应用进行了优化。该项目计划于2019年下半年开始风险生产纵观半导体供应链,包括IC代工、晶圆碰撞、IC载体、PCB(印刷电路板)和OSAT(海外组装和测试)等,由于传统产业的诸多原因,IC载体和PCB技术的尺寸缩放远远落后于IC代工。在下一代互连中,业界需要各种各样的突破方法来扩大通带线的规模。传统的有机衬底在制造和高密度I/ o中面临许多翘曲,表面粗糙度和材料尺寸稳定性问题,具有非常精细的线互连。为了突破这些挑战,对玻璃载体材料、新型光成像介质(PID)和先进设备进行了细线和细孔互连的评价。在本文中,对许多PID和非PID材料进行了调查和比较,用于细通孔(< 10μm)互连或高频低损耗应用。第一个候选材料被选择用于再分配层(RDL)的制造,使用370mm × 470mm的玻璃板。采用半添加工艺(SAP)对不同介电材料的玻璃板进行直接金属化,形成菊花链试验车。雏菊链的工艺、制造集成和电学测量结果表明,雏菊链在玻璃板衬底中具有良好的连续性和电阻性。本研究还对热循环试验(TCT)和高加速应力试验(HAST)的可靠性进行了评价。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Advanced Packaging Technology for Novel 1-dimensional and 2-dimensional VCSEL Arrays The Pivotal Role of Uniformity of Electrolytic Deposition Processes to Improve the Reliability of Advanced Packaging Enhancing the Paste Release on 55μm pads with Water-Soluble Type 7 SAC305 Solder Paste for High Density SIP Application Coronavirus, chip boom, and supply shortage: The new normal for global semiconductor manufacturing Lithography Solutions for Submicron Panel-Level Packaging
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1