Oscillatory 2-neuron sub-network design and performance based on sub-threshold CMOS operation

Abstract

Spiking neural networks are capable for efficient solutions of Constrained Graphical Optimization problems like the Travelling Salesman Problem (TSP). Such networks employ a sub-net of two coupled neuron with synchronous (in phase) and complementary (out of phase) spiking oscillations. A recent demonstration of energy efficient CMOS neurons based on sub-threshold operation enables low power hardware implementation for such networks. Here we demonstrate a circuit-level simulation of such two-neuron network by low-power sub-threshold CMOS design for neuron using a 65 nm technology and demonstrate complementary spiking oscillations. To design the hardware, in addition to the neuron, peripheral circuitry of Spike Driver, Crossbar array and Synaptic Unit is added to incorporate network synaptic dynamics. Our two-neuron one-synapse integrated network has 2.5 times less energy than a two-neuron system in literature. We estimate its area and find energy consumption of peripheral circuitry to be 2% of the implemented neuron. Such sub-net designs performance are stepping stones to design and estimate the performance of large-scale neural networks for neuromorphic hardware based optimization problems.