Novel Frequency Synthesizer for Spur Level Reduction

Abstract

A novel frequency synthesizer architecture for reducing spur level is presented. By using a feedforward path a new zero in the transfer function is generated which enables us to increase the capacitor tied to the control voltage line and thus reducing spur level. A fast settling technique is also used to compensate the effect of spur reduction technique on settling time. Different blocks of frequency synthesizer are implemented in MATLAB/Simulink. Simulations show 13 dB improvement in reference spur level compared to conventional architecture for a 2.4 GHz frequency synthesizer.