Probabilistic error modeling for sequential logic

Abstract

Reliability is a crucial issue in nanoscale devices including both CMOS (beyond 22 nm) and non-CMOS. Devices in this regime tend to be more prone to errors due to thermal effects creating uncertainty in device characteristics. The transient nature of these errors commands the need for a probabilistic model that can represent the inherent circuit logic and can measure the errors. In sequential logic the error occurred in a particular time frame will be propagated to consecutive time frames thereby making the device more volatile. Any model that can represent a sequential logic should handle both spatial dependencies between nodes in a single time slice and temporal dependencies between nodes of different time slices. While modeling error in sequential logic the complexity arises in handling the temporal dependencies due to the feedback. Essentially, the feedback makes the system non-causal where outputs depend not only on inputs but also its own previous values. Depending on the circuit structure and the nature of feedback, various circuits would offer different degree of temporal dependence. In this work we propose a probabilistic error model for sequential logic that can measure the average output error probability that account for the spatio-temporal nature of the inherent dependencies using an temporally evolving causal Bayesian Networks also called Dynamic Bayesian Networks.