An optimized gate-loop layout for multi-chip SiC MOSFET power modules

Abstract

This paper investigates the impact of gate-loop layouts on the switching loss of a multi-chip silicon carbide metal-oxide-semiconductor field-effect-transistor (MSOFET) power module. Six gate loop layouts are proposed and evaluated in switching simulations. A 16.2% difference on the total switching loss is observed between a good and a bad gate loop layout. The results shows that the total switching loss can be reduced with a "reverse matching arrangement" between the gate loop and the power loop. Specifically, to assign a short gate loop to the device that has a large power-loop inductance, and vice versa. In addition, shared traces from the gate driver to the paralleled devices could further reduce the total switching loss.