Pub Date : 2015-12-30DOI: 10.1109/WIPDA.2015.7369312
S. Mazumder, J. Leach, K. Udwary, K. Technologies, Xinmei Wang
This manuscript provides a brief outline on a relatively new line of work with focus on optically-switched GaN based devices.
这份手稿提供了一个相对较新的工作线的简要概述，重点是基于光开关GaN的器件。
{"title":"Recent developments in GaN-based optical rapid switching semiconductor devices","authors":"S. Mazumder, J. Leach, K. Udwary, K. Technologies, Xinmei Wang","doi":"10.1109/WIPDA.2015.7369312","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369312","url":null,"abstract":"This manuscript provides a brief outline on a relatively new line of work with focus on optically-switched GaN based devices.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"9 1","pages":"66-69"},"PeriodicalIF":0.0,"publicationDate":"2015-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89710902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369309
R. Singh, B. Grummel, S. Sundaresan
Short-circuit (SC) robustness of 1200 V-rated SiC npn Junction Transistors (SJTs) and commercial power DMOSFETs is investigated. Due to low overdrive base currents and low short-circuit currents the absence of short-channel effects, SJTs demonstrate superior SC capability including: (a) minimum short-circuit withstand time (tSc) of 14 μs, even at Vds=1000 V (b) Perfectly stable output and blocking characteristics after the application of 10,000, 10 μs long SC pulses at 800 V, and (c) tSC ≥ 18 μs at 800 V up to (at-least) 175°C base-plate temperatures. In contrast, commercial (Gen-II) 1200 V/80 mΩ SiC MOSFETs exhibit catastrophic failure beyond tSC = 7 μs at 500 V, and tSC = 3 μs at 800 V, due to excessive SC currents of > 200 A resulting in junction temperatures in excess of 650°C. Also, the MOSFET's drain leakage currents increase by a factor of 120, and the Vth reduces by 20%, after the application of 7 μs-long SC pulses at 500 V. Electro-thermal simulations indicate a significantly lower junction temperature for SJTs during short circuit pulses as compared to SiC MOSFETs.
{"title":"Short circuit robustness of 1200 V SiC switches","authors":"R. Singh, B. Grummel, S. Sundaresan","doi":"10.1109/WIPDA.2015.7369309","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369309","url":null,"abstract":"Short-circuit (SC) robustness of 1200 V-rated SiC npn Junction Transistors (SJTs) and commercial power DMOSFETs is investigated. Due to low overdrive base currents and low short-circuit currents the absence of short-channel effects, SJTs demonstrate superior SC capability including: (a) minimum short-circuit withstand time (tSc) of 14 μs, even at Vds=1000 V (b) Perfectly stable output and blocking characteristics after the application of 10,000, 10 μs long SC pulses at 800 V, and (c) tSC ≥ 18 μs at 800 V up to (at-least) 175°C base-plate temperatures. In contrast, commercial (Gen-II) 1200 V/80 mΩ SiC MOSFETs exhibit catastrophic failure beyond tSC = 7 μs at 500 V, and tSC = 3 μs at 800 V, due to excessive SC currents of > 200 A resulting in junction temperatures in excess of 650°C. Also, the MOSFET's drain leakage currents increase by a factor of 120, and the Vth reduces by 20%, after the application of 7 μs-long SC pulses at 500 V. Electro-thermal simulations indicate a significantly lower junction temperature for SJTs during short circuit pulses as compared to SiC MOSFETs.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"39 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74371748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369294
C. Dimarino, B. Hull
This paper reports the avalanche capabilities of commercial 1.2 kV SiC MOSFETs. Various non-repetitive avalanche conditions, such as current, energy, and time in avalanche, were tested in order to fully evaluate the ruggedness of the SiC MOSFETs. From this testing, a boundary was drawn to identify the typical avalanche ruggedness of each device. It was shown that, unlike similarly-rated Si CoolMOS devices, the SiC MOSFETs could withstand avalanche currents that are more than twice that of their rated current. It was also determined that the avalanche boundary is scalable to the entire family of Cree's 1.2 kV SiC MOSFETs by the device active area. This is a noteworthy characteristic of the Cree SiC MOSFETs, as it indicates consistent behavior among the different devices.
本文报道了商用1.2 kV SiC mosfet的雪崩性能。为了充分评估SiC mosfet的坚固性，测试了各种非重复雪崩条件，如雪崩中的电流、能量和时间。从这个测试中，绘制了一个边界来确定每个设备的典型雪崩坚固性。结果表明，与类似额定的Si CoolMOS器件不同，SiC mosfet可以承受超过其额定电流两倍的雪崩电流。还确定雪崩边界可扩展到Cree的整个1.2 kV SiC mosfet系列的器件有效面积。这是Cree SiC mosfet的一个值得注意的特性，因为它表明不同器件之间的行为一致。
{"title":"Characterization and prediction of the avalanche performance of 1.2 kV SiC MOSFETs","authors":"C. Dimarino, B. Hull","doi":"10.1109/WIPDA.2015.7369294","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369294","url":null,"abstract":"This paper reports the avalanche capabilities of commercial 1.2 kV SiC MOSFETs. Various non-repetitive avalanche conditions, such as current, energy, and time in avalanche, were tested in order to fully evaluate the ruggedness of the SiC MOSFETs. From this testing, a boundary was drawn to identify the typical avalanche ruggedness of each device. It was shown that, unlike similarly-rated Si CoolMOS devices, the SiC MOSFETs could withstand avalanche currents that are more than twice that of their rated current. It was also determined that the avalanche boundary is scalable to the entire family of Cree's 1.2 kV SiC MOSFETs by the device active area. This is a noteworthy characteristic of the Cree SiC MOSFETs, as it indicates consistent behavior among the different devices.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"35 1","pages":"263-267"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79354144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369288
S. Bolte, N. Frohleke, J. Bocker
In this contribution, a 1 kW one phase power factor correction (PFC) rectifier with a Gallium Nitride (GaN) transistor is optimized considering switching frequency in regard to the losses of the PFC inductor. A driver circuit with negative voltage at switch-off supplied from a unipolar voltage supply is proposed. A model of the PFC rectifier including conduction and switching losses of semiconductors, copper and core losses of inductor is developed and utilized to identify the best design by numeric optimization of switching frequency, number of turns and length of air gap. Simulation results show an efficiency of about 98.6% at full load with 230 V mains voltage.
{"title":"Efficiency optimization for a power factor correction (PFC) rectifier with gallium nitride transistor","authors":"S. Bolte, N. Frohleke, J. Bocker","doi":"10.1109/WIPDA.2015.7369288","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369288","url":null,"abstract":"In this contribution, a 1 kW one phase power factor correction (PFC) rectifier with a Gallium Nitride (GaN) transistor is optimized considering switching frequency in regard to the losses of the PFC inductor. A driver circuit with negative voltage at switch-off supplied from a unipolar voltage supply is proposed. A model of the PFC rectifier including conduction and switching losses of semiconductors, copper and core losses of inductor is developed and utilized to identify the best design by numeric optimization of switching frequency, number of turns and length of air gap. Simulation results show an efficiency of about 98.6% at full load with 230 V mains voltage.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"309 1","pages":"220-223"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88305772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369283
H. O’Brien, A. Ogunniyi, W. Shaheen, S. Ryu
This research is focused on characterization of the turn-on transition of high voltage SiC thyristors of different epilayer thicknesses and active area sizes to determine their suitability and limitations in high-dI/dt, fast-switching applications. The unique aspects of this study include the very high current density being switched through the thyristors over a short period of time at initial turn-on, resulting in very high instantaneous dissipated power over the small device volume. The devices that were characterized were 6 kV, 0.5 cm2 super gate turn-off thyristors (SGTOs), 10 kV, 1.05 cm2 SGTOs, and 15 kV, 1.05 cm2 SGTOs, all fabricated by Cree, Inc. for the Army Research Laboratory. The highest dI/dt and current density were 13 kA/microsecond and 3.2 kA/cm2 for a parallel pair of 0.5 cm2 thyristors, with pulse current peaking 250 ns from initial gate trigger. These evaluations help determine tradeoffs between series-stacking two lower-voltage thyristors versus using a single thicker-epi device, or paralleling two small-area devices versus switching one larger device, for fast-switching applications.
{"title":"Study of the turn-on of various high-voltage SiC thyristors","authors":"H. O’Brien, A. Ogunniyi, W. Shaheen, S. Ryu","doi":"10.1109/WIPDA.2015.7369283","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369283","url":null,"abstract":"This research is focused on characterization of the turn-on transition of high voltage SiC thyristors of different epilayer thicknesses and active area sizes to determine their suitability and limitations in high-dI/dt, fast-switching applications. The unique aspects of this study include the very high current density being switched through the thyristors over a short period of time at initial turn-on, resulting in very high instantaneous dissipated power over the small device volume. The devices that were characterized were 6 kV, 0.5 cm2 super gate turn-off thyristors (SGTOs), 10 kV, 1.05 cm2 SGTOs, and 15 kV, 1.05 cm2 SGTOs, all fabricated by Cree, Inc. for the Army Research Laboratory. The highest dI/dt and current density were 13 kA/microsecond and 3.2 kA/cm2 for a parallel pair of 0.5 cm2 thyristors, with pulse current peaking 250 ns from initial gate trigger. These evaluations help determine tradeoffs between series-stacking two lower-voltage thyristors versus using a single thicker-epi device, or paralleling two small-area devices versus switching one larger device, for fast-switching applications.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"73 1","pages":"5-9"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82876141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369314
Xuning Zhang, Nidhi Haryani, Zhiyu Shen, R. Burgos, D. Boroyevich
This paper presents an improved phase leg power loop design for enhance mode lateral structure Gallium Nitride (GaN) transistors. Static characterization results of a 650V/30A GaN transistor are presented. The gate driver circuit is designed based on the characterization results. In order to reduce current commutation loop inductance within the GaN phase leg, an improved power loop design with vertical structure is proposed for lateral structure GaN transistors. The control of Common Mode (CM) noise current propagation is also considered during the gate driver design by optimizing the power distribution and grounding structure of the gate driver and digital control circuits. By differentiating the propagation path impedance of digital control circuits and their power supply circuits, conductive CM noise can propagate through power supply path to protect the digital control circuits. The design is verified through experiments on a phase leg prototype which prove the effectiveness of the proposed phase leg on the overvoltage reduction during current transition along with less cross-coupling between power loop and gate loop compared with conventional lateral power loop design. Finally, a three phase motor drive system is designed and tested based on the proposed phase leg.
{"title":"Ultra-low inductance phase leg design for GaN-based three-phase motor drive systems","authors":"Xuning Zhang, Nidhi Haryani, Zhiyu Shen, R. Burgos, D. Boroyevich","doi":"10.1109/WIPDA.2015.7369314","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369314","url":null,"abstract":"This paper presents an improved phase leg power loop design for enhance mode lateral structure Gallium Nitride (GaN) transistors. Static characterization results of a 650V/30A GaN transistor are presented. The gate driver circuit is designed based on the characterization results. In order to reduce current commutation loop inductance within the GaN phase leg, an improved power loop design with vertical structure is proposed for lateral structure GaN transistors. The control of Common Mode (CM) noise current propagation is also considered during the gate driver design by optimizing the power distribution and grounding structure of the gate driver and digital control circuits. By differentiating the propagation path impedance of digital control circuits and their power supply circuits, conductive CM noise can propagate through power supply path to protect the digital control circuits. The design is verified through experiments on a phase leg prototype which prove the effectiveness of the proposed phase leg on the overvoltage reduction during current transition along with less cross-coupling between power loop and gate loop compared with conventional lateral power loop design. Finally, a three phase motor drive system is designed and tested based on the proposed phase leg.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"5 1","pages":"119-124"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91469306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369282
D. Reusch
Power converters are constantly trending towards higher efficiency, higher power density, higher switching frequency, and higher output current. Rapidly maturing gallium nitride (GaN) technology can meet these demands, and in this paper high performance 12 VIN to 1 VOUT eGaN monolithic half bridge IC based point-of-load (POL) buck converters will be demonstrated at output currents up to 40 A and switching frequencies up to 4 MHz.
{"title":"High frequency eGaN monolithic half bridge IC based 12 VIN to 1 VOUT point of load converter","authors":"D. Reusch","doi":"10.1109/WIPDA.2015.7369282","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369282","url":null,"abstract":"Power converters are constantly trending towards higher efficiency, higher power density, higher switching frequency, and higher output current. Rapidly maturing gallium nitride (GaN) technology can meet these demands, and in this paper high performance 12 VIN to 1 VOUT eGaN monolithic half bridge IC based point-of-load (POL) buck converters will be demonstrated at output currents up to 40 A and switching frequencies up to 4 MHz.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"163 4 1","pages":"371-376"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86667783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369285
Mehrdad Biglarbegian, Neel Shah, I. Mazhari, B. Parkhideh
This paper presents the design and implementation of high power density and highly efficient air-core embedded inductor onto Printed Circuit Board (PCB) for 280W-5A/240nH, 280W-12A/150nH and 280W-18A/50nH. The toroidal structure due to its better performance on interfacing electromagnetic fields (EMI), is investigated. In addition, thermal restrictions are considered at high current capacity by reducing the inductor size. This will bring the advantage of lower resistivity and consequently the conduction loss. Other challenges such as temperature rise optimization of high current (18A) on the PCB is also investigated. First, parameter calculation for design consideration of an embedded inductor are presented, then JMAG simulations are used to observe precisely the temperature rise profile distribution in different sections of the inductor. An optimized design to achieve high efficient inductor and simultaneously high power density is proposed and several experiments and accurate designs are shown. The primary results show an acceptable temperature rise for high current (18A) inductor without the heat sink.
{"title":"Design considerations for high power density/efficient PCB embedded inductor","authors":"Mehrdad Biglarbegian, Neel Shah, I. Mazhari, B. Parkhideh","doi":"10.1109/WIPDA.2015.7369285","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369285","url":null,"abstract":"This paper presents the design and implementation of high power density and highly efficient air-core embedded inductor onto Printed Circuit Board (PCB) for 280W-5A/240nH, 280W-12A/150nH and 280W-18A/50nH. The toroidal structure due to its better performance on interfacing electromagnetic fields (EMI), is investigated. In addition, thermal restrictions are considered at high current capacity by reducing the inductor size. This will bring the advantage of lower resistivity and consequently the conduction loss. Other challenges such as temperature rise optimization of high current (18A) on the PCB is also investigated. First, parameter calculation for design consideration of an embedded inductor are presented, then JMAG simulations are used to observe precisely the temperature rise profile distribution in different sections of the inductor. An optimized design to achieve high efficient inductor and simultaneously high power density is proposed and several experiments and accurate designs are shown. The primary results show an acceptable temperature rise for high current (18A) inductor without the heat sink.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"62 1","pages":"247-252"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73828842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369276
V. Pala, B. Hull, J. Richmond, P. Butler, S. Allen, J. Palmour
This paper presents a methodology to establish and qualify safe bounds of operation for Silicon Carbide power devices under avalanche stress. The methodology involves using a statistical method to estimate an avalanche safe operating area, and by ensuring that device reliability is not degraded after avalanche stress. We also demonstrate the avalanche capability of the C3M 900V SiC MOSFETs, which have been fully qualified for avalanche ruggedness by employing this methodology.
本文提出了一种建立和确定雪崩应力下碳化硅功率器件安全工作边界的方法。该方法包括使用统计方法来估计雪崩安全操作区域，并确保雪崩应力后设备可靠性不会降低。我们还展示了C3M 900V SiC mosfet的雪崩能力，通过采用这种方法，它已经完全符合雪崩坚固性。
{"title":"Methodology to qualify silicon carbide MOSFETs for single shot avalanche events","authors":"V. Pala, B. Hull, J. Richmond, P. Butler, S. Allen, J. Palmour","doi":"10.1109/WIPDA.2015.7369276","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369276","url":null,"abstract":"This paper presents a methodology to establish and qualify safe bounds of operation for Silicon Carbide power devices under avalanche stress. The methodology involves using a statistical method to estimate an avalanche safe operating area, and by ensuring that device reliability is not degraded after avalanche stress. We also demonstrate the avalanche capability of the C3M 900V SiC MOSFETs, which have been fully qualified for avalanche ruggedness by employing this methodology.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"56 1","pages":"56-59"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84552036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369295
Xuan Li, Liqi Zhang, Suxuan Guo, Yang Lei, A. Huang, Bo Zhang
Due to the limitation in circuit measurements using current and voltage probes, the conventional ways of measuring switching losses lack the physical insight of the complicated witching process in power devices such as the SiC power MOSFET. This paper seeks to have a better understanding of the dynamic turn-on and turn-off processes of the SiC power MOSFET. Using a detailed finite element simulation model in TCAD Sentaurus, a better and accurate understanding of switching losses in SiC MOSFET is obtained. The physical insights during switching process, as well as the impact of gate resistance and common source parasitic inductance are studied. Based on the results obtained in this study, SiC MOSFET can achieve lossless switching for both turn-on and turn-off if certain conditions of its gate drive circuit and load current conditions are met. Therefore this analysis provides a theoretical guidance for high voltage SiC MOSFETs to be used in extremely high switching frequency applications.
{"title":"Understanding switching losses in SiC MOSFET: Toward lossless switching","authors":"Xuan Li, Liqi Zhang, Suxuan Guo, Yang Lei, A. Huang, Bo Zhang","doi":"10.1109/WIPDA.2015.7369295","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369295","url":null,"abstract":"Due to the limitation in circuit measurements using current and voltage probes, the conventional ways of measuring switching losses lack the physical insight of the complicated witching process in power devices such as the SiC power MOSFET. This paper seeks to have a better understanding of the dynamic turn-on and turn-off processes of the SiC power MOSFET. Using a detailed finite element simulation model in TCAD Sentaurus, a better and accurate understanding of switching losses in SiC MOSFET is obtained. The physical insights during switching process, as well as the impact of gate resistance and common source parasitic inductance are studied. Based on the results obtained in this study, SiC MOSFET can achieve lossless switching for both turn-on and turn-off if certain conditions of its gate drive circuit and load current conditions are met. Therefore this analysis provides a theoretical guidance for high voltage SiC MOSFETs to be used in extremely high switching frequency applications.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"76 1","pages":"257-262"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83872993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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