A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

D. El-Damak, Saurav Bandyopadhyay, A. Chandrakasan
{"title":"A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors","authors":"D. El-Damak, Saurav Bandyopadhyay, A. Chandrakasan","doi":"10.1109/ISSCC.2013.6487776","DOIUrl":null,"url":null,"abstract":"Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"20 1","pages":"374-375"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"110","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2013.6487776","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 110

Abstract

Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection.
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采用片上铁电电容器的93%效率可重构开关电容DC-DC变换器
动态电压缩放(DVS)通过以满足所需性能的最小电压为电路模块供电,已成为系统节能运行的标准技术之一[1]。开关电容(SC) DC-DC转换器作为一种有前途的集成能量转换解决方案已经获得了极大的兴趣,该解决方案消除了对电感的需求[2,3]。然而,SC变换器的效率受到传导损耗、底板寄生电容、栅极驱动损耗以及控制电路开销的限制。支持多增益设置的可重构SC转换器已被提出,以允许在宽输出范围内高效运行[2,4]。此外,在[5]中使用了具有低底板寄生电容的高密度深沟电容器,其峰值效率可达90%。在这项工作中,我们利用片上铁电电容器(Fe-Caps)的高密度和极低的底板寄生电容进行电荷转移[6]。在可重构的动态增益选择架构中,将Fe-Caps与多增益设置转换器相结合,实现了高效率的转换。
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