Session 25 Overview: DRAM Memory Subcommittee

Abstract

First devices for the new DRAM standards LPDDR5 and DDR5 are implementing improvements in bandwidth and power efficiency. The new devices will have a huge impact on a very wide range of applications, from IoT applications and smartphones to server and workstation applications. A new proposal for managed LRDIMM promises to reduce cost and power, and to provide capacities up to 512GB. For next generation DRAM interfaces a PAM-3 transceiver with 27Gb/s/pin on the base of 3 bits per 2 symbols is presented. -generation LPDDR5 the maximum bandwidth as WCK clocking and non-target ODT (NT-ODT). power consumption using techniques such as dynamic voltage frequency scaling (DVFS), and a deep-sleep mode (DSM). presents a DDR5 SDRAM to overcome bandwidth, power and capacity limitations of DDR4. This paper presents a 16Gb 6.4Gb/s/pin DDR5 SDRAM with a phase-rotator-based DLL, write-level training, and RX/TX with the enhanced DFE/FFE. The energy efficiency is improved by more than 30% with 1.1V/1.8V VDD and VPP. a 3bit/2UI 1.03pJ/bit PAM-3 single-ended TRX. An 27Gb/s PAM-3 symbol is generated with an output driver voltage of 0.6V and a 1/3-rate forwarded clock frequency of 9GHz. The RX adopts a 1-tap tri-level DFE, which has the same complexity as for NRZ signaling to equalize the PAM-3 signal. Fabricated in a 28nm CMOS technology, the proposed PAM-3 TRX can be utilized for the next generation memory interface with low power. (ODP) structured (media) and ODP structure of for cost minimization, pre-CMD scheme for reduction. Dies per wafer increase of compared to conventional DRAM with same process and same capacity was achieved. DIMM power consumption is