X. Xue, Wenxiang Jian, Jianguo Yang, F. Xiao, Gang Chen, X. L. Xu, Yufeng Xie, Yinyin Lin, R. Huang, Qingtian Zhou, Jingang Wu
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引用次数: 31
Abstract
A 0.13μm 8Mb CuxSiyO resistive memory test macro with 20F2 cell size is developed based on logic process for the first time. Smart and adaptive assist write and read circuit are proposed and verified in order to fix yield and power consumption issues from large write speed and high temperature resistance variation. SAWM (self-adaptive write mode) helps to enlarge Roff/Ron window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and large power consumption is eliminated after set success. SARM (Self-adaptive read mode) improves read bit yield from 98% to 100% at 125°C. The typical access time of on-pitch voltage sensing SA(sense amplifier) is 21ns and high bandwidth throughput is supported.
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