A. Debnath, Sreenidhi Turuvekre, N. Dasgupta, A. DasGupta
{"title":"Charge Based Compact Modeling of Gate Leakage Mechanism in AlGaN/GaN HEMTs","authors":"A. Debnath, Sreenidhi Turuvekre, N. Dasgupta, A. DasGupta","doi":"10.1109/icee44586.2018.8937997","DOIUrl":null,"url":null,"abstract":"The gate leakage mechanism in AlGaN/GaN high electron mobility transistors (HEMT) is studied analytically using a charge-based model over a wide range of bias and temperature. Three distinct current mechanisms, Poole-Frenkel (PF), Defect assisted tunneling (DAT) and Thermionic emission (TE) are modeled. PF is the significant mechanism in reverse bias, while TE and DAT are the two dominant mechanisms in forward and low reverse bias respectively. This model is implemented in Verilog-A and rigorously validated with experimental data.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"175 1","pages":"1-5"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icee44586.2018.8937997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The gate leakage mechanism in AlGaN/GaN high electron mobility transistors (HEMT) is studied analytically using a charge-based model over a wide range of bias and temperature. Three distinct current mechanisms, Poole-Frenkel (PF), Defect assisted tunneling (DAT) and Thermionic emission (TE) are modeled. PF is the significant mechanism in reverse bias, while TE and DAT are the two dominant mechanisms in forward and low reverse bias respectively. This model is implemented in Verilog-A and rigorously validated with experimental data.