Impact of Asymmetric Memory Hole Profile on Silicon Selective Epitaxial Growth in 3D NAND Memory : AEPM: Advanced Equipment Processes and Materials

Abstract

For silicon selective epitaxy growth (Si-SEG) process, an ex situ pre-epitaxial treatment (PET) is applied in order to remove the damaged layer and impurities. In this work, we observe asymmetric Si recess formed at the bottom of vertical channel (VC) holes in varied staircase environments leading to non-uniform, poor Si-SEG quality. A proposed symmetric silicon oxide/nitride (ON) film stack environment around VC holes by a given REG shift or via applicable layout modification manages to provide balanced charging potential to form symmetric Si etched recess inside VC holes post PET process. Subsequently, the Si-SEG process can form uniform epitaxial Si height at the bottom of VC in 3D NAND fabrication.