Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185213
Shiladitya Chakravorty, N. Nagarur
In semiconductor manufacturing fabs, presence of queue time restricted zones within manufacturing routes present some unique challenges for fab dispatching and scheduling systems. In this study we discuss some of these challenges and present a cycle time prediction methodology based on backpropagation trained artificial neural network which can be used for making real time dispatching decisions at trigger steps of queue time restricted zones.
{"title":"An Artificial Neural Network Based Algorithm For Real Time Dispatching Decisions","authors":"Shiladitya Chakravorty, N. Nagarur","doi":"10.1109/ASMC49169.2020.9185213","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185213","url":null,"abstract":"In semiconductor manufacturing fabs, presence of queue time restricted zones within manufacturing routes present some unique challenges for fab dispatching and scheduling systems. In this study we discuss some of these challenges and present a cycle time prediction methodology based on backpropagation trained artificial neural network which can be used for making real time dispatching decisions at trigger steps of queue time restricted zones.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"18 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73214541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185358
R. Attota
Using only two derived numbers based on a reference library, this paper shows how through-focus scanning optical microscopy (TSOM) is compatible with computational process control (CPC) for the complete 3Dshape process monitoring of nanoscale to microscale targets. This is demonstrated using three types of target switch widths (CDs) and depths ranging from 50 nm to1.0 μm, and 70 nm to 20 μm, respectively. TSOM is a high through put, low-cost and in-line capable optical dimensional metrology method ideally suited for high volume manufacturing (HVM), complementing other widely used metrology tools.
{"title":"Computational Process Control Compatible Dimensional Metrology Tool: Through-focus Scanning Optical Microscopy","authors":"R. Attota","doi":"10.1109/ASMC49169.2020.9185358","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185358","url":null,"abstract":"Using only two derived numbers based on a reference library, this paper shows how through-focus scanning optical microscopy (TSOM) is compatible with computational process control (CPC) for the complete 3Dshape process monitoring of nanoscale to microscale targets. This is demonstrated using three types of target switch widths (CDs) and depths ranging from 50 nm to1.0 μm, and 70 nm to 20 μm, respectively. TSOM is a high through put, low-cost and in-line capable optical dimensional metrology method ideally suited for high volume manufacturing (HVM), complementing other widely used metrology tools.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 7 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72687199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185193
YongSung Ji, Jee-Hyong Lee
Semiconductor wafer map data provides valuable information for semiconductor engineers. Correctly classified defect patterns in wafer maps can increase semiconductor productivity. Convolutional Neural Networks (CNN) achieved excellent performance on computer vision and were frequently used method in wafer map classification. The CNN-based classifier of the wafer map defect pattern requires a sufficiently large training set to ensure high performance. However, for the real semiconductor production environment, it is challenging to collect various defect patterns enough. In this paper, we propose a method to supplement the lack of training set using Generative Adversarial Networks (GAN) to improve the performance of the classifier. We measure our performance on the ‘WM-811k’ dataset, which consists of 811K real-world wafer maps. We compare the performance of our classifiers with commonly used augmentation techniques. As a result, we achieved remarkable performance enhancement from 97.0% to 98.3%.
{"title":"Using GAN to Improve CNN Performance of Wafer Map Defect Type Classification : Yield Enhancement","authors":"YongSung Ji, Jee-Hyong Lee","doi":"10.1109/ASMC49169.2020.9185193","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185193","url":null,"abstract":"Semiconductor wafer map data provides valuable information for semiconductor engineers. Correctly classified defect patterns in wafer maps can increase semiconductor productivity. Convolutional Neural Networks (CNN) achieved excellent performance on computer vision and were frequently used method in wafer map classification. The CNN-based classifier of the wafer map defect pattern requires a sufficiently large training set to ensure high performance. However, for the real semiconductor production environment, it is challenging to collect various defect patterns enough. In this paper, we propose a method to supplement the lack of training set using Generative Adversarial Networks (GAN) to improve the performance of the classifier. We measure our performance on the ‘WM-811k’ dataset, which consists of 811K real-world wafer maps. We compare the performance of our classifiers with commonly used augmentation techniques. As a result, we achieved remarkable performance enhancement from 97.0% to 98.3%.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"50 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77889114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185400
R. V. Roijen, M. Lucksinger, M. Fields, R. Baiocco, M. Oh, Derek Stoll
Recent developments in the Semiconductor industry are moving away from the trend of transition to the next technology node, instead diversifying to address different markets. We discuss some implications of a change, which in our case involves a transition in chip size. Even when the node remains the same, changing the chip size affects process as well as process control and productivity. We discuss the effects of the introduction of products with a small chip size in a production line optimized for large Logic chips. We also describe specific changes made to optimize our Lithography, Reactive Ion Etching (RIE) and Chemical-Mechanical Polishing (CMP) process for small chips.
{"title":"Uniformity and Yield Optimization for a highly diverse Product Mix : Topic: YE","authors":"R. V. Roijen, M. Lucksinger, M. Fields, R. Baiocco, M. Oh, Derek Stoll","doi":"10.1109/ASMC49169.2020.9185400","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185400","url":null,"abstract":"Recent developments in the Semiconductor industry are moving away from the trend of transition to the next technology node, instead diversifying to address different markets. We discuss some implications of a change, which in our case involves a transition in chip size. Even when the node remains the same, changing the chip size affects process as well as process control and productivity. We discuss the effects of the introduction of products with a small chip size in a production line optimized for large Logic chips. We also describe specific changes made to optimize our Lithography, Reactive Ion Etching (RIE) and Chemical-Mechanical Polishing (CMP) process for small chips.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"40 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85804881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185331
So-Hui Park, Sungbin Lee, Eunsun Hong, B. Kim, Jihye Yi, Gyeom-Heon Kim, Jinho Kim, Jungdae Park
As the semiconductor process becomes more complicated, process monitoring that reflects real time process conditions is important. The mass spectrometer is an effective tool to represent the process by monitoring process chemical reaction in real time. In order to apply the mass spectrometer data as the process-related data, it is necessary to use the data mining technique to process the large amount of collected data. In this study, we find out the correlation between the mass spectrometer data collected in real time and the process data describing the device performance with the data mining technique. We developed an automatic data analysis model to reduce the repetitive work of the analysts and improve the analysis efficiency about a large amount of the mass spectrometer data. We will contribute making a fault detection & classification system for fine control process by using advanced data analysis technology.
{"title":"A Data Mining Technique for Real Time Process Monitoring with Mass Spectrometry : APC: Advanced Process Control","authors":"So-Hui Park, Sungbin Lee, Eunsun Hong, B. Kim, Jihye Yi, Gyeom-Heon Kim, Jinho Kim, Jungdae Park","doi":"10.1109/ASMC49169.2020.9185331","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185331","url":null,"abstract":"As the semiconductor process becomes more complicated, process monitoring that reflects real time process conditions is important. The mass spectrometer is an effective tool to represent the process by monitoring process chemical reaction in real time. In order to apply the mass spectrometer data as the process-related data, it is necessary to use the data mining technique to process the large amount of collected data. In this study, we find out the correlation between the mass spectrometer data collected in real time and the process data describing the device performance with the data mining technique. We developed an automatic data analysis model to reduce the repetitive work of the analysts and improve the analysis efficiency about a large amount of the mass spectrometer data. We will contribute making a fault detection & classification system for fine control process by using advanced data analysis technology.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81351269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185242
Rajhans Singh, Ravi Garg, Nital S. Patel, M. W. Braun
Defect detection and classification is a critical step in any semiconductor manufacturing process. Most of the time it involves manual creation of defects which is time consuming and includes a high material and labor cost. In this paper we propose Artificial Intelligence-based synthetic defect generation techniques to augment the training image sets for Convolutional Neural Network (CNNs)-based defect detection and classification systems. Specifically, we use Generative Adversarial Networks (GANs) to create various modes of the defects which are difficult to create manually. Our results indicate that the output of our adapted GANs are images of realistic-looking defects for a wide variety of common manufacturing defects including foreign material, misplaced epoxy, scratches, and die chipping defects among others.
{"title":"Generative Adversarial Networks for Synthetic Defect Generation in Assembly and Test Manufacturing","authors":"Rajhans Singh, Ravi Garg, Nital S. Patel, M. W. Braun","doi":"10.1109/ASMC49169.2020.9185242","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185242","url":null,"abstract":"Defect detection and classification is a critical step in any semiconductor manufacturing process. Most of the time it involves manual creation of defects which is time consuming and includes a high material and labor cost. In this paper we propose Artificial Intelligence-based synthetic defect generation techniques to augment the training image sets for Convolutional Neural Network (CNNs)-based defect detection and classification systems. Specifically, we use Generative Adversarial Networks (GANs) to create various modes of the defects which are difficult to create manually. Our results indicate that the output of our adapted GANs are images of realistic-looking defects for a wide variety of common manufacturing defects including foreign material, misplaced epoxy, scratches, and die chipping defects among others.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"11 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87070083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185395
Haoshu Cai, Jianshe Feng, J. Moyne, Jimmy Iskandar, M. Armacost, Fei Li, J. Lee
In today’s microelectronics manufacturing facilities, fault detection (FD) is pervasive as the primary advanced process control (APC) capability in use. The current approach to FD, while effective, has a number of shortcomings that impact its cost and effectiveness. The highest among these is the cost in time and resources associated with the largely manual methods used for partitioning and extraction of features of interest in individual traces. Additionally, once these features are extracted, feature-based univariate analysis (UVA) is the primary method used for process monitoring and FD, which fails to incorporate process variable correlations in detecting faults and quality issues. On the other hand, current multivariate analysis (MVA) approaches, such as principal component analysis (PCA), partial least squares (PLS), and their variants, focus on threshold setting in a multivariate space so that they cannot provide direct limit settings on raw (sensor) parameters for decision-making support during online process monitoring. Also, in bypassing feature identification and extraction, the subject matter expert (SME) is largely left out of the loop in MVA analysis; thus, information on the relationship between univariate features and faults is not captured. Furthermore, it is difficult to visualize and understand multivariate limits due to the high dimensionality of the data produced in microelectronics manufacturing processes. Finally, slow and normal process changes often occur in real processes, which can lead to false alarms during implementation when using models trained from offline samples. Thus, a need exists for an FD method that leverages the existing feature-based UVA and provides (1) a method for automated signal partitioning and feature extraction that allows for SME input, (2) an MVA mechanism which considers correlation among parameters and is adaptive to the normal process drift, (3) an automatic approach for limiting UVA features that captures the correlation among parameters, and (4) a methodology for easily viewing these capabilities so that an SME is able to view, understand, and continue to contribute to the FD optimization process. This capability has been developed and successfully applied to microelectronics manufacturing data sets and is proposed as a key component to future microelectronics smart manufacturing systems.
{"title":"A Framework for Semi-Automated Fault Detection Configuration with Automated Feature Extraction and Limits Setting","authors":"Haoshu Cai, Jianshe Feng, J. Moyne, Jimmy Iskandar, M. Armacost, Fei Li, J. Lee","doi":"10.1109/ASMC49169.2020.9185395","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185395","url":null,"abstract":"In today’s microelectronics manufacturing facilities, fault detection (FD) is pervasive as the primary advanced process control (APC) capability in use. The current approach to FD, while effective, has a number of shortcomings that impact its cost and effectiveness. The highest among these is the cost in time and resources associated with the largely manual methods used for partitioning and extraction of features of interest in individual traces. Additionally, once these features are extracted, feature-based univariate analysis (UVA) is the primary method used for process monitoring and FD, which fails to incorporate process variable correlations in detecting faults and quality issues. On the other hand, current multivariate analysis (MVA) approaches, such as principal component analysis (PCA), partial least squares (PLS), and their variants, focus on threshold setting in a multivariate space so that they cannot provide direct limit settings on raw (sensor) parameters for decision-making support during online process monitoring. Also, in bypassing feature identification and extraction, the subject matter expert (SME) is largely left out of the loop in MVA analysis; thus, information on the relationship between univariate features and faults is not captured. Furthermore, it is difficult to visualize and understand multivariate limits due to the high dimensionality of the data produced in microelectronics manufacturing processes. Finally, slow and normal process changes often occur in real processes, which can lead to false alarms during implementation when using models trained from offline samples. Thus, a need exists for an FD method that leverages the existing feature-based UVA and provides (1) a method for automated signal partitioning and feature extraction that allows for SME input, (2) an MVA mechanism which considers correlation among parameters and is adaptive to the normal process drift, (3) an automatic approach for limiting UVA features that captures the correlation among parameters, and (4) a methodology for easily viewing these capabilities so that an SME is able to view, understand, and continue to contribute to the FD optimization process. This capability has been developed and successfully applied to microelectronics manufacturing data sets and is proposed as a key component to future microelectronics smart manufacturing systems.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"134 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73280937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185285
K. Matam, B. Peethala, C. Taff, Z. Gardner, Chung Ju Yang, Sankar Muthumanickam, D. Sil
The published paper will discuss the impact of exhaust pressure and velocity on particle performance in wet clean process chambers. Correlations are drawn from chamber exhaust pressure, exhaust velocity, and exhaust duct condition to explain the observed degradation in particle performance. Based on the observations, key solutions including periodic preventative maintenance on exhaust duct lines, chamber wipe downs, exhaust rebalancing are recommended to improve chamber stability and particle performance.
{"title":"Impact of Process Chambers Exhaust on Wafer Defectivity in Wet Clean tools","authors":"K. Matam, B. Peethala, C. Taff, Z. Gardner, Chung Ju Yang, Sankar Muthumanickam, D. Sil","doi":"10.1109/ASMC49169.2020.9185285","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185285","url":null,"abstract":"The published paper will discuss the impact of exhaust pressure and velocity on particle performance in wet clean process chambers. Correlations are drawn from chamber exhaust pressure, exhaust velocity, and exhaust duct condition to explain the observed degradation in particle performance. Based on the observations, key solutions including periodic preventative maintenance on exhaust duct lines, chamber wipe downs, exhaust rebalancing are recommended to improve chamber stability and particle performance.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"47 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73779475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185300
Hyojeong Seo, Jeonghye Yang, Y. J. Ma, Jongwoo Park, Mi Kyoung Kim, D. Seo, S. J. Yoon, Sang Jong Park
We present the reduction in number of post process particles by use of YF3 coatings on an alumina plasma reactor for fluorine chemistry based dry cleaning. With the introduction of highly reactive gases such as fluorine in semiconductor dry cleaning processes, especially within highly energetic plasmas, physical and chemical reactions between equipment parts and process gases continues to become an issue. Unaccounted for compounds and microstructures on tools leads to increasing particle defects on product wafers. The plasma density and ion energy is especially high at the dielectric walls of the remote plasma source (RPS). By utilizing a 150 micron YF3 layer to coat the plasma dielectric walls of our high selectivity oxide removal tool, we were able to eliminate the formation of AlOx Fy microstructures on the ceramic reactor surface, which in turn led to a greater than 85% reduction of “spark”-like particle contaminants near the centers of product wafer surface. Meanwhile electrical properties, etch rates, and selectivity were largely unaffected when compared to uncoated reactors. Surface profiler measurements showed an increase in surface roughness after coating, however a large reduction in reactor surface etch depth was shown after several hundred hours of processing. Furthermore, AlOx Fy particles were not detected by Energy Dispersive X-Ray Spectroscopy (EDS) on wafers processed with the YF3 coated RPS, in contrast to results from uncoated sources.
{"title":"Particle Defect Reduction Through YF3 Coated Remote Plasma Source for High Throughput Dry Cleaning Process","authors":"Hyojeong Seo, Jeonghye Yang, Y. J. Ma, Jongwoo Park, Mi Kyoung Kim, D. Seo, S. J. Yoon, Sang Jong Park","doi":"10.1109/ASMC49169.2020.9185300","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185300","url":null,"abstract":"We present the reduction in number of post process particles by use of YF3 coatings on an alumina plasma reactor for fluorine chemistry based dry cleaning. With the introduction of highly reactive gases such as fluorine in semiconductor dry cleaning processes, especially within highly energetic plasmas, physical and chemical reactions between equipment parts and process gases continues to become an issue. Unaccounted for compounds and microstructures on tools leads to increasing particle defects on product wafers. The plasma density and ion energy is especially high at the dielectric walls of the remote plasma source (RPS). By utilizing a 150 micron YF3 layer to coat the plasma dielectric walls of our high selectivity oxide removal tool, we were able to eliminate the formation of AlOx Fy microstructures on the ceramic reactor surface, which in turn led to a greater than 85% reduction of “spark”-like particle contaminants near the centers of product wafer surface. Meanwhile electrical properties, etch rates, and selectivity were largely unaffected when compared to uncoated reactors. Surface profiler measurements showed an increase in surface roughness after coating, however a large reduction in reactor surface etch depth was shown after several hundred hours of processing. Furthermore, AlOx Fy particles were not detected by Energy Dispersive X-Ray Spectroscopy (EDS) on wafers processed with the YF3 coated RPS, in contrast to results from uncoated sources.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"11 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79689658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Defect control is an important part of semiconductor manufacturing as it ensures device quality. In general, defect control is accomplished using numerous types of inspection equipment to find excursion wafers or process tools and help identify the defect source during production. However, the balance between productivity and inspection needs to be calculated carefully to minimize the manufacturing cost. In general, achieving high productivity is the priority for a semiconductor factory, requiring inspection cost saving while still maintaining stable device yield. As one of the many inspection points, all incoming test wafers are qualified by unpatterned wafer defect inspectors, which raises cost concerns for manufacturing. Extending test wafer reuse lifetime is a common target for cost savings. In this paper, an advanced inspection methodology is described to achieve the maximum recycling extension of nitride (Si3 N4) deposited wafers. The inspection bottleneck of the recycling extension is not only related to increased surface roughness after film removal, but also to the inspected sensitivity shift value between pre-and post-scans. The Surfscan® SP3 and Surfscan® SP5 unpatterned wafer defect inspection systems are used for the study of recycling extension of test wafers. Furthermore, the technique of defect source analysis (DSA) is utilized to identify the suitable pre-scan sensitivity for the zero false adder goal. In summary, the optimization of the inspector’s aperture configuration for post-scan inspection can minimize the sensitivity shift value. Based on the evaluated Si3 N4 layers, 26nm pre-scan sensitivity is required to avoid false adders. Furthermore, the Surfscan SP5 is the preferred platform over the Surfscan SP3 due to the better suppression of haze and a 3x faster throughput. Up to $5 sim 7$ wafer recycle times for test wafers can be achieved for the demonstrated Si3 N4 layers, which can save 84% incoming wafer purchasing.
{"title":"Advanced Inspection Methodology for the Maximum Extension of Nitride Test Wafer Recycling","authors":"Yu-Yuan Ke, Kuang-Hsiu Chen, Shin-Ru Chen, Guan-Wei Huang, Wesley Yu, Po-Jen Chuang, Chun-Li Lin, Chih-Wei Huang, J. Chen, Shao-Ju Chang, Nachiketa Janardan, Tung-Ying Lee, E. Chen, Chao-Yu Cheng","doi":"10.1109/ASMC49169.2020.9185221","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185221","url":null,"abstract":"Defect control is an important part of semiconductor manufacturing as it ensures device quality. In general, defect control is accomplished using numerous types of inspection equipment to find excursion wafers or process tools and help identify the defect source during production. However, the balance between productivity and inspection needs to be calculated carefully to minimize the manufacturing cost. In general, achieving high productivity is the priority for a semiconductor factory, requiring inspection cost saving while still maintaining stable device yield. As one of the many inspection points, all incoming test wafers are qualified by unpatterned wafer defect inspectors, which raises cost concerns for manufacturing. Extending test wafer reuse lifetime is a common target for cost savings. In this paper, an advanced inspection methodology is described to achieve the maximum recycling extension of nitride (Si3 N4) deposited wafers. The inspection bottleneck of the recycling extension is not only related to increased surface roughness after film removal, but also to the inspected sensitivity shift value between pre-and post-scans. The Surfscan® SP3 and Surfscan® SP5 unpatterned wafer defect inspection systems are used for the study of recycling extension of test wafers. Furthermore, the technique of defect source analysis (DSA) is utilized to identify the suitable pre-scan sensitivity for the zero false adder goal. In summary, the optimization of the inspector’s aperture configuration for post-scan inspection can minimize the sensitivity shift value. Based on the evaluated Si3 N4 layers, 26nm pre-scan sensitivity is required to avoid false adders. Furthermore, the Surfscan SP5 is the preferred platform over the Surfscan SP3 due to the better suppression of haze and a 3x faster throughput. Up to $5 sim 7$ wafer recycle times for test wafers can be achieved for the demonstrated Si3 N4 layers, which can save 84% incoming wafer purchasing.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"10 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84941485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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