Virtual prototyping of R2D NASIC based FPGA

Abstract

Application developers request safe and reliable layers on which to operate. Reliability has been assumed for years, as CMOS circuits were correct-by-construction. Nowadays, shrinking transistor size implies a reduction in yield and reliability of SoC, due to the presence or appearance of physical defects in the circuit. Nanotechnologies face same issues and despite many efforts for yield improvement, circuits remain unreliable. Rethinking the methodologies and design tools becomes now critical. We promote the use of FPGA-like overlay architectures, that offer a stable layer over time for application designers, while embedding fault-mitigation techniques that depend on the underlying technology.