Emerging technologies are under research for future VLSI circuits. Memristor crossbar is one of the promising candidates due to its scalability, non-volatility, etc. Non-volatile logic circuits based on memristor crossbar have been proposed recently. However, these logic circuits can merely map a single building block (e.g., 1-bit full adder) on a crossbar, and how to map multiple building blocks on a crossbar is not addressed, which is crucial to implement a VLSI circuit. This paper proposes a scheme to map multiple building blocks on memristor crossbar, which can simultaneously optimize the delay for each block. In addition, two techniques to optimize the design in terms of delay, area and power consumption are proposed. To illustrate the potential of the proposed mapping scheme, multi-bit adders are used as a case study; their delay, area and power costs for both crossbar and its CMOS controller are evaluated. The results show that the optimized designs reduce area (>23%), delay (>26%) and power consumption (>21%) as compared to initial designs. Finally, our designs are compared with state-of-the-art.
{"title":"Mosaic: A scheme of mapping non-volatile Boolean logic on memristor crossbar","authors":"Lei Xie","doi":"10.1145/2950067.2950088","DOIUrl":"https://doi.org/10.1145/2950067.2950088","url":null,"abstract":"Emerging technologies are under research for future VLSI circuits. Memristor crossbar is one of the promising candidates due to its scalability, non-volatility, etc. Non-volatile logic circuits based on memristor crossbar have been proposed recently. However, these logic circuits can merely map a single building block (e.g., 1-bit full adder) on a crossbar, and how to map multiple building blocks on a crossbar is not addressed, which is crucial to implement a VLSI circuit. This paper proposes a scheme to map multiple building blocks on memristor crossbar, which can simultaneously optimize the delay for each block. In addition, two techniques to optimize the design in terms of delay, area and power consumption are proposed. To illustrate the potential of the proposed mapping scheme, multi-bit adders are used as a case study; their delay, area and power costs for both crossbar and its CMOS controller are evaluated. The results show that the optimized designs reduce area (>23%), delay (>26%) and power consumption (>21%) as compared to initial designs. Finally, our designs are compared with state-of-the-art.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"82 1","pages":"91-96"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87607506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the need of data-intensive (or big data) applications is growing, the exascale system (i.e., capable of executing 1018 operations per second) is desired. However, it is challenging to scale von Neumann architecture to meet this need, due to its unavoidable data movement between processors and memories. To address such a challenge, this paper proposes a local-processing computer architecture (MECRO) based on memristor crossbar, which consists both microarchitecture and instruction set. Differing from von Neumann architecture, MECRO executes all operations locally in the memristor-based memory using stateful logic operations, where the same devices simultaneously serve as both logic and memory. In addition, this paper proposes a new multiplication arithmetic algorithm that is suitable for MECRO. n×n matrix multiplication is used as example of data-intensive applications. MECRO is verified with SPICE simulations in a small scale. Comparing with a von Neumann architecture consisting of p processors, the experiment shows that MECRO is able to improve the execution time in an order of O(n2/p), while using the similar memory (O(n3)).
{"title":"MECRO: A local processing computer architecture based on memristor crossbar","authors":"Lei Xie, M. A. Haron","doi":"10.1145/2950067.2950099","DOIUrl":"https://doi.org/10.1145/2950067.2950099","url":null,"abstract":"As the need of data-intensive (or big data) applications is growing, the exascale system (i.e., capable of executing 1018 operations per second) is desired. However, it is challenging to scale von Neumann architecture to meet this need, due to its unavoidable data movement between processors and memories. To address such a challenge, this paper proposes a local-processing computer architecture (MECRO) based on memristor crossbar, which consists both microarchitecture and instruction set. Differing from von Neumann architecture, MECRO executes all operations locally in the memristor-based memory using stateful logic operations, where the same devices simultaneously serve as both logic and memory. In addition, this paper proposes a new multiplication arithmetic algorithm that is suitable for MECRO. n×n matrix multiplication is used as example of data-intensive applications. MECRO is verified with SPICE simulations in a small scale. Comparing with a von Neumann architecture consisting of p processors, the experiment shows that MECRO is able to improve the execution time in an order of O(n2/p), while using the similar memory (O(n3)).","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"29 1","pages":"85-90"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80480737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. B. Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. Wang, D. Ravelosona
Current induced domain walls (DW) motion in magnetic nanowires or nano-stripes presents a novel approach to store and convey data. Combining with magnetic tunnel junction (MTJ) nanopillars, Racetrack memory (RM) becomes a new class of non-volatile memory thanks to its large storage capacity and fast data access. However, we need a relatively high current passing through the nanowire to move magnetic domain walls. This leads to a big challenge to design integration circuits and architecture for RM beyond the device level research. For instance, we find that the resistivity of nanowire material is a very critical parameter for the RM design. In this paper, we present the design of racetrack memory taking into account the physical prospects of magnetic domain wall motion in nanowires. By using an industrial CMOS 40 nm design kit and a perpendicular magnetic anisotropy (PMA) RM compact model, mixed SPICE simulations have been performed to analyze the area (e.g. 1 F2), speed and reliability performances.
{"title":"Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires","authors":"N. B. Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. Wang, D. Ravelosona","doi":"10.1145/2770287.2770305","DOIUrl":"https://doi.org/10.1145/2770287.2770305","url":null,"abstract":"Current induced domain walls (DW) motion in magnetic nanowires or nano-stripes presents a novel approach to store and convey data. Combining with magnetic tunnel junction (MTJ) nanopillars, Racetrack memory (RM) becomes a new class of non-volatile memory thanks to its large storage capacity and fast data access. However, we need a relatively high current passing through the nanowire to move magnetic domain walls. This leads to a big challenge to design integration circuits and architecture for RM beyond the device level research. For instance, we find that the resistivity of nanowire material is a very critical parameter for the RM design. In this paper, we present the design of racetrack memory taking into account the physical prospects of magnetic domain wall motion in nanowires. By using an industrial CMOS 40 nm design kit and a perpendicular magnetic anisotropy (PMA) RM compact model, mixed SPICE simulations have been performed to analyze the area (e.g. 1 F2), speed and reliability performances.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"125 1","pages":"71-76"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85701637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Content addressable memory is a novel storage device that can save data in its cells, which could be read, written and searched on the basis of their contents. This paper presents Memristor content addressable memory (M-CAM) structures that are formed of M-CAM cells, which compare searched data and stored data then give a cell output signal to be kept in its comparator. After the comparison in each cell, reading is enabled at each row of all comparators. The current of each row could be measured, if some comparators are high resistance (0) in a row, the current of that row could be lower than the current from another row where all comparators are low resistance (1), which means the corresponding row is a match. The main emphasis of this paper is to highlight the process of the M-CAM comparison and how to get the match entry. Our experimental results show that M-CAM is able to not only query accurately, but also fuzzy lookup through setting the memristor off-to-on resistance ratio.
{"title":"Memristor content addressable memory","authors":"Wanlong Chen, X. Yang, Frank Z. Wang","doi":"10.1145/2770287.2770308","DOIUrl":"https://doi.org/10.1145/2770287.2770308","url":null,"abstract":"Content addressable memory is a novel storage device that can save data in its cells, which could be read, written and searched on the basis of their contents. This paper presents Memristor content addressable memory (M-CAM) structures that are formed of M-CAM cells, which compare searched data and stored data then give a cell output signal to be kept in its comparator. After the comparison in each cell, reading is enabled at each row of all comparators. The current of each row could be measured, if some comparators are high resistance (0) in a row, the current of that row could be lower than the current from another row where all comparators are low resistance (1), which means the corresponding row is a match. The main emphasis of this paper is to highlight the process of the M-CAM comparison and how to get the match entry. Our experimental results show that M-CAM is able to not only query accurately, but also fuzzy lookup through setting the memristor off-to-on resistance ratio.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"29 1","pages":"83-87"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76067642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Payvand, Justin Rofeh, A. Sodhi, L. Theogarajan
Memristors have proven to be powerful analogs of neural synapses. While there have been some efforts to exploit this feature, the intrinsic analog nature of the memristive element has not been fully utilized. This paper presents a hardware-efficient neuromorphic CMOS-memristor pattern classifier. The system takes advantage of the memristor as a true analog memory, and Spike Timing Dependent Plasticity (STDP) is utilized to program memristors in a recurrent neural network. System co-simulations are performed in Verilog-AMS with CMOS devices and previously published memristive models. The results indicate the power of this approach in pattern classification using unsupervised learning.
{"title":"A CMOS-memristive self-learning neural network for pattern classification applications","authors":"M. Payvand, Justin Rofeh, A. Sodhi, L. Theogarajan","doi":"10.1145/2770287.2770311","DOIUrl":"https://doi.org/10.1145/2770287.2770311","url":null,"abstract":"Memristors have proven to be powerful analogs of neural synapses. While there have been some efforts to exploit this feature, the intrinsic analog nature of the memristive element has not been fully utilized. This paper presents a hardware-efficient neuromorphic CMOS-memristor pattern classifier. The system takes advantage of the memristor as a true analog memory, and Spike Timing Dependent Plasticity (STDP) is utilized to program memristors in a recurrent neural network. System co-simulations are performed in Verilog-AMS with CMOS devices and previously published memristive models. The results indicate the power of this approach in pattern classification using unsupervised learning.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"108 1","pages":"92-97"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74655170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David Roclin, O. Bichler, C. Gamrat, Jacques-Olivier Klein
In this paper, we study the effects of sneak paths and parasitic metal line resistance in arrays of CBRAM memristive devices operating as synapses for spiking neural networks. Three structures of crosspoint array are reviewed: the crossbar (1R), the anode connected matrix (1T-IR) and the cathode connected matrix (1T-IR). We show that the crossbar is an energy-consuming structure with high leakage during SET/RESET and with an increased switching time due to voltage drops along the lines. Furthermore, we show that parasitic line resistance can have a significant impact on the read resistance of the devices, depending on their location in the crossbar.
{"title":"Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks","authors":"David Roclin, O. Bichler, C. Gamrat, Jacques-Olivier Klein","doi":"10.1145/2770287.2770291","DOIUrl":"https://doi.org/10.1145/2770287.2770291","url":null,"abstract":"In this paper, we study the effects of sneak paths and parasitic metal line resistance in arrays of CBRAM memristive devices operating as synapses for spiking neural networks. Three structures of crosspoint array are reviewed: the crossbar (1R), the anode connected matrix (1T-IR) and the cathode connected matrix (1T-IR). We show that the crossbar is an energy-consuming structure with high leakage during SET/RESET and with an increased switching time due to voltage drops along the lines. Furthermore, we show that parasitic line resistance can have a significant impact on the read resistance of the devices, depending on their location in the crossbar.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"95 1","pages":"13-18"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76100062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Memristors promise a means for very compact neu-romorphic nanoscale architectures that leverage in-situ learning algorithms. While traditional learning algorithms simulated in software commonly assume analog values for synaptic weights, actual physical memristors may have a finite set of achievable states during online learning. In this paper we simulate a learning algorithm with limitations on both the resolution of its weights and the means of switching between them to gain an appreciation for how these properties might affect classification performance. For our experiments we use the Locally Competitive Algorithm (LCA) by Rozell et al. in conjunction with the MNIST dataset. We investigate the effects of both linear and non-linear distributions of weight states, concluding that as long as the weights are roughly within a power law distribution close to linear the algorithm is still effective. Our results also show that the resolution required from a device depends on its transition function between states; for transitions akin to round to nearest, synaptic weights should have around 16 possible states (4-bit resolution) to obtain optimal results. We find that lowering the threshold required to change states or adding stochasticity to the system can reduce that requirement down to 4 states (2-bit resolution). The outcomes of our research are relevant for building neuromorphic hardware with state-of-the art memristive devices.
{"title":"On the influence of synaptic weight states in a locally competitive algorithm for memristive hardware","authors":"Walt Woods, Jens Bürger, C. Teuscher","doi":"10.1145/2770287.2770292","DOIUrl":"https://doi.org/10.1145/2770287.2770292","url":null,"abstract":"Memristors promise a means for very compact neu-romorphic nanoscale architectures that leverage in-situ learning algorithms. While traditional learning algorithms simulated in software commonly assume analog values for synaptic weights, actual physical memristors may have a finite set of achievable states during online learning. In this paper we simulate a learning algorithm with limitations on both the resolution of its weights and the means of switching between them to gain an appreciation for how these properties might affect classification performance. For our experiments we use the Locally Competitive Algorithm (LCA) by Rozell et al. in conjunction with the MNIST dataset. We investigate the effects of both linear and non-linear distributions of weight states, concluding that as long as the weights are roughly within a power law distribution close to linear the algorithm is still effective. Our results also show that the resolution required from a device depends on its transition function between states; for transitions akin to round to nearest, synaptic weights should have around 16 possible states (4-bit resolution) to obtain optimal results. We find that lowering the threshold required to change states or adding stochasticity to the system can reduce that requirement down to 4 states (2-bit resolution). The outcomes of our research are relevant for building neuromorphic hardware with state-of-the art memristive devices.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"38 1","pages":"19-24"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87068088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Tittmann, S. Hermann, S. Schulz, A. Pacheco-Sánchez, M. Claus, M. Schröter
Back-gated carbon nanotube field-effect transistors have been fabricated using a wafer-level technology. Source and drain electrodes are structured by lift-off and wet etching. AFM measurements reveal residual contaminations originating from structuring processes. We investigate the particle removal by an oxygen plasma treatment depending on the process time. I/V characterization reveals a strong dependency of transistor characteristics, especially hysteresis behavior, on surface cleanliness. We find the removal of residual particles to be much more important than a passivation to keep water molecules from the transistor region. We show hysteresis-free transistor behavior even after 9 weeks of storage in air without passivation.
{"title":"Hysteresis-free carbon nanotube field-effect transistors without passivation","authors":"J. Tittmann, S. Hermann, S. Schulz, A. Pacheco-Sánchez, M. Claus, M. Schröter","doi":"10.1145/2770287.2770320","DOIUrl":"https://doi.org/10.1145/2770287.2770320","url":null,"abstract":"Back-gated carbon nanotube field-effect transistors have been fabricated using a wafer-level technology. Source and drain electrodes are structured by lift-off and wet etching. AFM measurements reveal residual contaminations originating from structuring processes. We investigate the particle removal by an oxygen plasma treatment depending on the process time. I/V characterization reveals a strong dependency of transistor characteristics, especially hysteresis behavior, on surface cleanliness. We find the removal of residual particles to be much more important than a passivation to keep water molecules from the transistor region. We show hysteresis-free transistor behavior even after 9 weeks of storage in air without passivation.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"51 1","pages":"137-138"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88745913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Djaafar Chabi, Zhaohao Wang, Weisheng Zhao, Jacques-Olivier Klein
The memristor-based neural learning network is considered as one of the candidates for future computing systems thanks to its low power, high density and defect-tolerance. However, its application is still hindered by the limitations of huge neuron structure and complicated learning cell. In this paper, we present a memristor-based neural crossbar circuit to implement on-chip supervised learning rule. In our work, activation function of neuron is implemented with simple CMOS inverter to save area overhead. Importantly, we propose a compact learning cell with a crossbar latch consisting of two antiparallel oriented binary memristors. This scheme allows high density integration and could improve the reliability of learning circuit. We describe firstly the circuit architecture, memristor model and operation process of supervised learning rule. Afterwards we perform transient simulation with CMOS 40nm design kit to validate the function of proposed learning circuit. Analysis and evaluation demonstrate that our circuit show great potential in on-chip learning.
{"title":"On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron","authors":"Djaafar Chabi, Zhaohao Wang, Weisheng Zhao, Jacques-Olivier Klein","doi":"10.1145/2770287.2770290","DOIUrl":"https://doi.org/10.1145/2770287.2770290","url":null,"abstract":"The memristor-based neural learning network is considered as one of the candidates for future computing systems thanks to its low power, high density and defect-tolerance. However, its application is still hindered by the limitations of huge neuron structure and complicated learning cell. In this paper, we present a memristor-based neural crossbar circuit to implement on-chip supervised learning rule. In our work, activation function of neuron is implemented with simple CMOS inverter to save area overhead. Importantly, we propose a compact learning cell with a crossbar latch consisting of two antiparallel oriented binary memristors. This scheme allows high density integration and could improve the reliability of learning circuit. We describe firstly the circuit architecture, memristor model and operation process of supervised learning rule. Afterwards we perform transient simulation with CMOS 40nm design kit to validate the function of proposed learning circuit. Analysis and evaluation demonstrate that our circuit show great potential in on-chip learning.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"41 1","pages":"7-12"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86835809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Zahir, Syed Azhar Ali Zaidi, A. Pulimeno, M. Graziano, D. Demarchi, G. Masera, G. Piccinini
Molecular devices have been proposed as an alternative solution for the design and fabrication of complex logic functions. In this paper a hybrid model of the molecular transistor (MT) is used to simulate different logic circuits. The model is based on the density function theory (DFT) combined with the Non Equilibrium Greens Function (NEGF) to find the transmission spectrum (TS) at equilibrium. The self-consistent method is used to calculate the I-V characteristics at nonequilibrium condition, considering the more realistic case of broadening of energy levels under the assumption of strong molecule electrode coupling. We have used a four terminal device with source, drain and two gate electrodes: one (backgate) used to increase the ION/IOFF ratio and the other as normal control gate. The very same device is contextualized in the case of a structure feasible with currently available technology and several technological parameters are used to explore the solution space. This ensemble has been described and simulated using VHDL-AMS and allowed the design of a library of logic cells e.g NAND, NOR, Inverter and Half Adder suitable for architecture design. Results are given on both the modeling level and the circuits functional performance. Our findings represent an important breakthrough in the state of the art 1) for the methodology and design flow used and 2) for the detailed understanding on the device analyzed and optimized with the point of view of the circuit designer.
{"title":"Molecular transistor circuits: From device model to circuit simulation","authors":"A. Zahir, Syed Azhar Ali Zaidi, A. Pulimeno, M. Graziano, D. Demarchi, G. Masera, G. Piccinini","doi":"10.1145/2770287.2770318","DOIUrl":"https://doi.org/10.1145/2770287.2770318","url":null,"abstract":"Molecular devices have been proposed as an alternative solution for the design and fabrication of complex logic functions. In this paper a hybrid model of the molecular transistor (MT) is used to simulate different logic circuits. The model is based on the density function theory (DFT) combined with the Non Equilibrium Greens Function (NEGF) to find the transmission spectrum (TS) at equilibrium. The self-consistent method is used to calculate the I-V characteristics at nonequilibrium condition, considering the more realistic case of broadening of energy levels under the assumption of strong molecule electrode coupling. We have used a four terminal device with source, drain and two gate electrodes: one (backgate) used to increase the ION/IOFF ratio and the other as normal control gate. The very same device is contextualized in the case of a structure feasible with currently available technology and several technological parameters are used to explore the solution space. This ensemble has been described and simulated using VHDL-AMS and allowed the design of a library of logic cells e.g NAND, NOR, Inverter and Half Adder suitable for architecture design. Results are given on both the modeling level and the circuits functional performance. Our findings represent an important breakthrough in the state of the art 1) for the methodology and design flow used and 2) for the detailed understanding on the device analyzed and optimized with the point of view of the circuit designer.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"22 1","pages":"129-134"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75865062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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