Co-Design and Optimization of a 320 GHz On-Chip Antenna for THz detection in 65nm CMOS Technology

Abstract

This paper presents design and optimization techniques to develop an on-chip array-feasible antenna for Terahertz (THz) detection at 320GHz using 65nm CMOS technology. Trade-offs between detector dimensions, thermal noise, and impedance matching have been considered, as well as design challenges related to manufacturing rules. The chosen antenna is a bow-tie and a ground plane has been employed to reduce substrates losses. Despite the complexity of achieving a high radiation efficiency erad, these techniques allow to obtain a good matching and efficiency that brings to a high responsivity for the detector. The effectiveness of these techniques has been validated using simulation results.