Pub Date : 2022-09-21DOI: 10.1109/icicdt56182.2022.9933087
S. Subhechha, N. Rassoul, A. Belmonte, H. Hody, H. Dekkers, Michiel J. van Setten, A. Chasin, S. H. Sharifi, K. Banerjee, H. Puliyalil, S. Kundu, M. Pak, D. Tsvetanova, N. Bazzazian, K. Vandersmissen, D. Batuk, J. Geypen, J. Heijlen, R. Delhougne, G. Kar
{"title":"Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control","authors":"S. Subhechha, N. Rassoul, A. Belmonte, H. Hody, H. Dekkers, Michiel J. van Setten, A. Chasin, S. H. Sharifi, K. Banerjee, H. Puliyalil, S. Kundu, M. Pak, D. Tsvetanova, N. Bazzazian, K. Vandersmissen, D. Batuk, J. Geypen, J. Heijlen, R. Delhougne, G. Kar","doi":"10.1109/icicdt56182.2022.9933087","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933087","url":null,"abstract":"","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"1 1","pages":"88"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83088706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626485
A. V. Radogna, S. Capone, L. Francioso, P. Siciliano, S. D’Amico
This paper presents a flexible data acquisition (DAQ) system targeted to aerospace applications. The system is able to acquire raw signals from resistive, capacitive and digital/pulsed output sensors. The flexibility in the read-out capability is made possible thanks to: (1) the adoption of an integrated analog front-end (AFE) circuit for the generic interfacing of resistive and capacitive sensors; (2) the adoption of the same time-to-digital conversion approach for all the connected sensors. The AFE implements the resistance/capacitance-to-time conversion by generating a square wave, whose period is proportional to resistance or capacitance values. The time-to-digital conversion is made by the timer peripheral of a generic microcontroller board, thus avoiding the analog-to-digital converter (ADC). The architecture of the proposed DAQ system is presented and the design of the AFE circuit is detailed with emphasis on the energy-per-measurement (EpM) performance. As an example of operation, a demonstrator with two NTC thermistors and an Hall effect sensor, is made and measurement results are shown.
{"title":"A Flexible Data Acquisition System for Aerospace Applications","authors":"A. V. Radogna, S. Capone, L. Francioso, P. Siciliano, S. D’Amico","doi":"10.1109/ICICDT51558.2021.9626485","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626485","url":null,"abstract":"This paper presents a flexible data acquisition (DAQ) system targeted to aerospace applications. The system is able to acquire raw signals from resistive, capacitive and digital/pulsed output sensors. The flexibility in the read-out capability is made possible thanks to: (1) the adoption of an integrated analog front-end (AFE) circuit for the generic interfacing of resistive and capacitive sensors; (2) the adoption of the same time-to-digital conversion approach for all the connected sensors. The AFE implements the resistance/capacitance-to-time conversion by generating a square wave, whose period is proportional to resistance or capacitance values. The time-to-digital conversion is made by the timer peripheral of a generic microcontroller board, thus avoiding the analog-to-digital converter (ADC). The architecture of the proposed DAQ system is presented and the design of the AFE circuit is detailed with emphasis on the energy-per-measurement (EpM) performance. As an example of operation, a demonstrator with two NTC thermistors and an Hall effect sensor, is made and measurement results are shown.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"17 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87882443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626482
J. Franco, H. Arimura, J. D. Marneffe, A. Vandooren, L. Ragnarsson, Zhicheng Wu, D. Claes, E. Litta, N. Horiguchi, K. Croes, D. Linten, T. Grasser, B. Kaczer
We discuss low thermal budget gate stack solutions for BTI reliability, compatible with novel stacked device integration schemes (e.g., Sequential 3D) and architectures (e.g., nanosheets, CFETs). Dipole formation at the interface between the SiO2 IL and the high-k dielectric improves the nMOS PBTI reliability and enables effective Work Function tuning with a single gate metal, without any sizable impact on the EOT and physical thickness of the gate stack. For pMOS, low temperature exposure of the SiO2 IL to atomic hydrogen before HKMG deposition is shown to largely improve NBTI reliability, outmatching conventional RMG solutions based on high temperature ‘reliability anneals’ or high-k first integration.
{"title":"Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper","authors":"J. Franco, H. Arimura, J. D. Marneffe, A. Vandooren, L. Ragnarsson, Zhicheng Wu, D. Claes, E. Litta, N. Horiguchi, K. Croes, D. Linten, T. Grasser, B. Kaczer","doi":"10.1109/ICICDT51558.2021.9626482","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626482","url":null,"abstract":"We discuss low thermal budget gate stack solutions for BTI reliability, compatible with novel stacked device integration schemes (e.g., Sequential 3D) and architectures (e.g., nanosheets, CFETs). Dipole formation at the interface between the SiO2 IL and the high-k dielectric improves the nMOS PBTI reliability and enables effective Work Function tuning with a single gate metal, without any sizable impact on the EOT and physical thickness of the gate stack. For pMOS, low temperature exposure of the SiO2 IL to atomic hydrogen before HKMG deposition is shown to largely improve NBTI reliability, outmatching conventional RMG solutions based on high temperature ‘reliability anneals’ or high-k first integration.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"32 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74971959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626470
G. Quarta, M. Perenzoni, S. D’Amico
This paper presents design and optimization techniques to develop an on-chip array-feasible antenna for Terahertz (THz) detection at 320GHz using 65nm CMOS technology. Trade-offs between detector dimensions, thermal noise, and impedance matching have been considered, as well as design challenges related to manufacturing rules. The chosen antenna is a bow-tie and a ground plane has been employed to reduce substrates losses. Despite the complexity of achieving a high radiation efficiency erad, these techniques allow to obtain a good matching and efficiency that brings to a high responsivity for the detector. The effectiveness of these techniques has been validated using simulation results.
{"title":"Co-Design and Optimization of a 320 GHz On-Chip Antenna for THz detection in 65nm CMOS Technology","authors":"G. Quarta, M. Perenzoni, S. D’Amico","doi":"10.1109/ICICDT51558.2021.9626470","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626470","url":null,"abstract":"This paper presents design and optimization techniques to develop an on-chip array-feasible antenna for Terahertz (THz) detection at 320GHz using 65nm CMOS technology. Trade-offs between detector dimensions, thermal noise, and impedance matching have been considered, as well as design challenges related to manufacturing rules. The chosen antenna is a bow-tie and a ground plane has been employed to reduce substrates losses. Despite the complexity of achieving a high radiation efficiency erad, these techniques allow to obtain a good matching and efficiency that brings to a high responsivity for the detector. The effectiveness of these techniques has been validated using simulation results.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"23 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76204378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626488
Conrad Guhl, S. Bott, I. Albayrak, Anne Weitzmann, R. Krause, Joscha Kappel, Birgit Reinhold, Nan Wu, M. Zier, A. Schüring, Hongwei Ma, R. Hüselitz, B. Uhlig, M. Wislicenus
In this contribution we present an approach upon process window evaluation based on different STI test chip designs. General applicable process rules are derived, which help IC design engineers to care for key process requirements of CMP without full process insights. Special focus is laid on the sensitivity of the polish process result in structured areas on surrounding densities as well as the impact of large regions with homogenous density e.g. pure field regions. In a case study we will present the application of these general results derived from test chip experiments to a designers demand. The change of STI density was highly desirable from a device point of view, but limited by design rules. Such design rules are often very strict to ensure a safe fabrication, however for device diversification the existing rules might be too strict. To work with (exceptions from) such strict design rules a detailed process understanding is needed. Based on test chip experiments design scenarios to avoid device problems due to CMP process restrictions have been derived.
{"title":"Design process interactions in shallow trench isolation chemical mechanical planarization for layout diversification and design optimization","authors":"Conrad Guhl, S. Bott, I. Albayrak, Anne Weitzmann, R. Krause, Joscha Kappel, Birgit Reinhold, Nan Wu, M. Zier, A. Schüring, Hongwei Ma, R. Hüselitz, B. Uhlig, M. Wislicenus","doi":"10.1109/ICICDT51558.2021.9626488","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626488","url":null,"abstract":"In this contribution we present an approach upon process window evaluation based on different STI test chip designs. General applicable process rules are derived, which help IC design engineers to care for key process requirements of CMP without full process insights. Special focus is laid on the sensitivity of the polish process result in structured areas on surrounding densities as well as the impact of large regions with homogenous density e.g. pure field regions. In a case study we will present the application of these general results derived from test chip experiments to a designers demand. The change of STI density was highly desirable from a device point of view, but limited by design rules. Such design rules are often very strict to ensure a safe fabrication, however for device diversification the existing rules might be too strict. To work with (exceptions from) such strict design rules a detailed process understanding is needed. Based on test chip experiments design scenarios to avoid device problems due to CMP process restrictions have been derived.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"146 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72773691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626463
He Peng, Qichao Yang, Yuqin Dou, R. Berenguer, Gui Liu
This paper presents a 76–81 GHz down-conversion mixer designed in 65 nm CMOS process. To enhance the load impedance and improve the transconductance (gm) of the transconductance stage, a novel mixer structure is proposed. The presented mixer includes an enhanced Gilbert-cell core with series peaking inductors for reducing noise and intermediate frequency (IF) buffer. The load stage is cross-coupled with PMOS transistors (CCPT) in parallel, and the gm stage is stacked with PMOS transistors (SPT). Under the power of 1 dBm local oscillator (LO), the input third-order intercept point (IIP3) is −8.34 dBm. The mixer consumes 8 mW under 1.2 V power supply. The LO-to-RF isolation is better than 40 dB at 76–81 GHz. At 77 GHz, the conversion gain (CG) and noise figure (NF) are 11.8 dB and 12.9 dB, respectively. Compared with conventional down-conversion mixers, the presented mixer is suitable for automotive radar with high CG and low NF.
{"title":"A 77GHz CMOS Down-Conversion Mixer with High CG Using CCPT-SPT Structure","authors":"He Peng, Qichao Yang, Yuqin Dou, R. Berenguer, Gui Liu","doi":"10.1109/ICICDT51558.2021.9626463","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626463","url":null,"abstract":"This paper presents a 76–81 GHz down-conversion mixer designed in 65 nm CMOS process. To enhance the load impedance and improve the transconductance (gm) of the transconductance stage, a novel mixer structure is proposed. The presented mixer includes an enhanced Gilbert-cell core with series peaking inductors for reducing noise and intermediate frequency (IF) buffer. The load stage is cross-coupled with PMOS transistors (CCPT) in parallel, and the gm stage is stacked with PMOS transistors (SPT). Under the power of 1 dBm local oscillator (LO), the input third-order intercept point (IIP3) is −8.34 dBm. The mixer consumes 8 mW under 1.2 V power supply. The LO-to-RF isolation is better than 40 dB at 76–81 GHz. At 77 GHz, the conversion gain (CG) and noise figure (NF) are 11.8 dB and 12.9 dB, respectively. Compared with conventional down-conversion mixers, the presented mixer is suitable for automotive radar with high CG and low NF.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"57 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74632185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626511
Chun Zhao, T. Zhao, Yixin Cao, Yina Liu, Li Yang, I. Mitrovic, E. G. Lim, Cezhou Zhao
For the past decades, the synaptic devices for the inmemory computing have been widely investigated due to the high-efficiency computing potential and the ability to mimic biological neurobehavior. However, the conventional twoterminal synaptic memristors show drawbacks of resistance reduction caused by large-scale paralleling and asynchronous storage-reading process, which limit its development. Recently, researchers have paid attention to the transistor-like artificial synapse. Due to the existence of insulator layer and the separation of input and read terminals, the three-terminal synaptic transistors are believed to have greater potential towards artificial intelligence (AI) application fields. In this work, a summary of recent progresses and the future challenges of synaptic transistors are discussed.
{"title":"Advanced synaptic transistor device towards AI application in hardware perspective","authors":"Chun Zhao, T. Zhao, Yixin Cao, Yina Liu, Li Yang, I. Mitrovic, E. G. Lim, Cezhou Zhao","doi":"10.1109/ICICDT51558.2021.9626511","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626511","url":null,"abstract":"For the past decades, the synaptic devices for the inmemory computing have been widely investigated due to the high-efficiency computing potential and the ability to mimic biological neurobehavior. However, the conventional twoterminal synaptic memristors show drawbacks of resistance reduction caused by large-scale paralleling and asynchronous storage-reading process, which limit its development. Recently, researchers have paid attention to the transistor-like artificial synapse. Due to the existence of insulator layer and the separation of input and read terminals, the three-terminal synaptic transistors are believed to have greater potential towards artificial intelligence (AI) application fields. In this work, a summary of recent progresses and the future challenges of synaptic transistors are discussed.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"9 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83358935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626481
Zhuocheng Wang, Ruize Sun
In this work, the reverse-blocking high electron mobility transistor with stepped p-type GaN drain (SPD RB-HEMT) is proposed in this paper. The reverse-blocking capability is achieved by employing a stepped p-type GaN layer connected with the drain metal. The SPD RB-HEMT shows a blocking rating over ±1800 V and on-resistance of 2.35 mΩ·cm2 in TCAD Sentaurus simulation. Meanwhile, the stepped p-type GaN drain can reduce the offset of the turn-on voltage and optimize the electric field. Compared with conventional RB-HEMTs, the proposed SPD RB-HEMT can realize improved and balanced forward and reverse blocking characteristics.
{"title":"Reverse Blocking HEMTs with Stepped P-GaN Drain","authors":"Zhuocheng Wang, Ruize Sun","doi":"10.1109/ICICDT51558.2021.9626481","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626481","url":null,"abstract":"In this work, the reverse-blocking high electron mobility transistor with stepped p-type GaN drain (SPD RB-HEMT) is proposed in this paper. The reverse-blocking capability is achieved by employing a stepped p-type GaN layer connected with the drain metal. The SPD RB-HEMT shows a blocking rating over ±1800 V and on-resistance of 2.35 mΩ·cm2 in TCAD Sentaurus simulation. Meanwhile, the stepped p-type GaN drain can reduce the offset of the turn-on voltage and optimize the electric field. Compared with conventional RB-HEMTs, the proposed SPD RB-HEMT can realize improved and balanced forward and reverse blocking characteristics.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88826648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper analyzed the hysteresis of effective output capacitance of GaN E-mode devices in overvoltage transients. The hysteresis of effective output capacitance as well as the current transformation between electron current and displacement current are studied by TCAD simulation. The dynamics of trapping in GaN material are illustrated to show the imbalance of stored and released charges in devices, so as to locate the origin of the hysteresis of effective output capacitance. This paper can provide insights into the energy loss of GaN E–mode devices in power conversion applications where overvoltage transients are endangering incidents, such as flyback converters.
{"title":"Dynamic Trapping Related Hysteresis of Effective Output Capacitance in Overvoltage Transients of GaN E-mode Devices","authors":"Ruize Sun, Jingxue Lai, Chao Liu, Wanjun Chen, Yiqiang Chen, Xingpeng Liu, Bo Zhang","doi":"10.1109/ICICDT51558.2021.9626506","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626506","url":null,"abstract":"This paper analyzed the hysteresis of effective output capacitance of GaN E-mode devices in overvoltage transients. The hysteresis of effective output capacitance as well as the current transformation between electron current and displacement current are studied by TCAD simulation. The dynamics of trapping in GaN material are illustrated to show the imbalance of stored and released charges in devices, so as to locate the origin of the hysteresis of effective output capacitance. This paper can provide insights into the energy loss of GaN E–mode devices in power conversion applications where overvoltage transients are endangering incidents, such as flyback converters.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"93 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83841084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626496
D. Dinulovic, M. Shousha, M. Haug
This paper shows the main aspects and possibility of magnetics on silicon technology as a new fabrication technology for the development of magnetic micro components for high switching frequency applications ranging from 1 MHz to 100 MHz.
{"title":"Magnetics on Silicon Technology Enabling High Switching Frequency Applications","authors":"D. Dinulovic, M. Shousha, M. Haug","doi":"10.1109/ICICDT51558.2021.9626496","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626496","url":null,"abstract":"This paper shows the main aspects and possibility of magnetics on silicon technology as a new fabrication technology for the development of magnetic micro components for high switching frequency applications ranging from 1 MHz to 100 MHz.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80452892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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