A 0.6V 2.9µW mixed-signal front-end for ECG monitoring

Marcus Yip, J. Bohorquez, A. Chandrakasan
{"title":"A 0.6V 2.9µW mixed-signal front-end for ECG monitoring","authors":"Marcus Yip, J. Bohorquez, A. Chandrakasan","doi":"10.1109/VLSIC.2012.6243792","DOIUrl":null,"url":null,"abstract":"This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-VT digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"316 1","pages":"66-67"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243792","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 22

Abstract

This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-VT digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.
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用于心电监护的0.6V 2.9µW混合信号前端
本文提出了一种混合信号心电前端,它使用积极的电压缩放来最大限度地提高功率效率,并促进与低压dsp的集成。使用混合信号反馈消除50/60Hz干扰,通过降低动态范围要求实现超低电压操作。模拟电路针对超低电压进行了优化,采用双dac架构的SAR ADC消除了对耗电的ADC缓冲器的需求。过采样和ΔΣ-modulation利用近vt数字处理,在不牺牲噪声性能和动态范围的情况下实现超低功耗操作。完全集成的前端采用0.18μm CMOS工艺,功耗为2.9μW,电压为0.6V。
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