Study of Electromigration Failure in Solder Interconnects under Low Frequency Pulsed Direct Current Condition

Abstract

This paper concerns the electromigration (EM) failure mechanisms in solder interconnects under low frequency pulsed direct current (DC) conditions. In our study, the accelerated EM tests of Wafer-level Chip Scale Package (WCSP or WLCSP) samples are conducted under 4 different pulsed DC conditions: 0.1 Hz pulsed DC with duty factors (DFs) of 33%, 50%, 75%, and 100% (DC). The result of our testing suggests that there are at least two competing factors affecting the failure rate in an opposite manner under pulsed DC EM conditions. Specifically, when compared with the cumulative damage model (estimates the damage only during the on period), the failure kinetics is found to be more accelerated at high DF and decelerated at a lower DF. This conclusion is drawn from the observation that the EM failure rate shows an extremely nonlinear relationship with the DF and also that the failure occurs faster under a high DF than under solely DC conditions, which is not possible without a mechanism assisting the EM failure. Furthermore, it is found that there is a 2- stage resistance change before EM failure, an indication of the change in the dominant failure mechanism. The results may indicate that the pulsed DC effect on the EM failure mechanism is far more complex than anticipated with the possible involvement of a damage mechanism other than EM such as thermal fatigue.