Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations

Abstract

Evaluating the robustness of circuits with respect to soft errors has become of utmost importance in many application areas. This evaluation must in most cases be refined taking into account the application characteristics in order to avoid too pessimistic results. The main approach used today at design time is based on fault injection campaigns. Emulation can be used to speed up the evaluations, but requires noticeable effort to implement the circuit prototype. This paper presents an approach based on an automated analysis of register lifetime, requiring only one functional simulation of the target application. The approach has been demonstrated on significant circuits. The results show that the proposed approach can be more efficient than emulation in terms of experimental time, without requiring any specific hardware and achieving a good accuracy. The global intrinsic robustness is evaluated and the most critical registers or execution cycles can also be identified with good confidence.