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2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献

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Keytone: Silent Data Corruptions at Scale 关键字:无声的数据破坏的规模
Pub Date : 2023-07-03 DOI: 10.1109/iolts59296.2023.10224872
H. Dixit
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引用次数: 0
Welcome 欢迎
Yili Fu, Hesheng Wang, Yantao Shen
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引用次数: 0
Field profiling & monitoring of payload transistors in FPGAs fpga中有效负载晶体管的现场分析与监测
Da Cheng, Amitava Majumdar, Xiaobao Wang, N. Chong
A new use for ring-oscillators (ROs) is proposed by which PMOS and NMOS transistor strengths can be measured and monitored in the field. A new metric, based on RO duty-cycle is defined. This new metric, along with RO-frequency, offers a way to profile and bin transistors based on their drive strengths. With ROs configured from payload transistors, along with the natural programmability of FPGAs, this strength based profiling can be done in the field at a level of granularity that is not possible with existing methodologies. New applications of the metrics and the profiling methodology include use of on-die ROs as a (a) monitor and control for duty-cycle sensitive designs, (b) replacement for scribe-line test structures, and (c) sensor for payload transistor characteristics over life-time.
提出了一种新的环形振荡器(ROs)的用途,通过它可以在现场测量和监测PMOS和NMOS晶体管的强度。定义了一个基于RO占空比的新度量。这个新的指标,连同ro频率,提供了一种基于驱动强度来分析和分类晶体管的方法。通过有效负载晶体管配置ROs,以及fpga的自然可编程性,这种基于强度的分析可以在现有方法无法实现的粒度级别上在现场完成。指标和分析方法的新应用包括使用片上ROs作为(a)占空比敏感设计的监视和控制,(b)替代划线测试结构,以及(c)有效载荷晶体管寿命特性传感器。
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引用次数: 2
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms 基于软件的错误检测机制的定时错误检测性能的硬件仿真相关性
Yutaka Masuda, M. Hashimoto, T. Onoye
Software-based error detection techniques, which includes EDM (error detection mechanisms) transformation, are used for error localization in post-silicon validation. This paper evaluates the performance of EDM for timing error localization with 65-nm test chips assuming the following two EDM usage scenarios; (1) localizing a timing error occurred in the original program, and (2) localizing potential timing errors that vary execution results. Experimental results show that the EDM transformation customized for quick error detection detects 25% of timing errors in the original program in the first scenario and 56% of non-masked errors in the second scenario. However, these hardware measurement results are not consistent with the simulation results of our previous work. To investigate the reason, we focus on the following two differences between hardware and simulation; (1) design of power distribution network, and (2) definition of timing error occurrence frequency. We update the simulation setup for filling the difference and re-execute the simulation. We confirm that the simulation and the chip measurement results are consistent, which validates our simulation methodology.
基于软件的错误检测技术,包括EDM(错误检测机制)转换,用于后硅验证中的错误定位。本文采用65nm测试芯片,在以下两种EDM使用场景下,评估了EDM在定时误差定位方面的性能;(1)定位原始程序中发生的计时错误,(2)定位不同执行结果的潜在计时错误。实验结果表明,为快速错误检测而定制的EDM变换在第一种场景下检测到原程序中25%的定时错误,在第二种场景下检测到56%的非屏蔽错误。然而,这些硬件测量结果与我们之前工作的仿真结果并不一致。为了探究其原因,我们重点关注硬件和仿真之间的以下两个差异;(1)配电网的设计;(2)定时误差发生频率的定义。我们更新模拟设置以填补差异并重新执行模拟。我们证实了仿真和芯片测量结果是一致的,这验证了我们的仿真方法。
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引用次数: 1
Tackling long duration transients in sequential logic 处理顺序逻辑中的长时间瞬态
Erol Koser, W. Stechele
Single Event Transients (SETs) in combinational logic remain to be an important topic in the reliability domain. SETs were traditionally relatively short in comparison to the clock period. The majority of the countermeasures utilizes this property. However, advances in technology scaling will reverse the ratio. Investigations show that SETs may last up to multiple clock cycles in the future. So called Long Duration Transients (LDTs) corrupt almost all available countermeasures. This work presents a new methodology to tackle LDTs. Dual Modular Redundancy (DMR) is used to detect any corruption of the application logic. A new micro-rollback scheme is introduced, that expands DMR-Architectures with correction capabilities. The concept is also capable of handling single event upsets and timing violations. The scheme utilizes a newly designed History Cell. The History Cell introduces an area overhead of 74% and a power overhead of 106% compared to a standard cell D-flip-flop. Area and power overheads for expanding an existing DMR-Architecture with correction capabilities are approximately 24% and 28%, respectively.
组合逻辑中的单事件瞬变(set)一直是可靠性领域的一个重要研究课题。与时钟周期相比,set通常相对较短。大多数对策都利用了这一特性。然而,技术的进步将扭转这一比例。研究表明,set在未来可能会持续多个时钟周期。所谓的长时间瞬变(LDTs)几乎破坏了所有可用的对抗措施。这项工作提出了一种解决最不发达国家问题的新方法。双模块冗余(Dual Modular Redundancy, DMR)用于检测应用程序逻辑的任何损坏。提出了一种新的微回滚方案,使dmr结构具有纠错能力。该概念还能够处理单个事件中断和时间违规。该方案采用了新设计的历史单元。与标准单元d触发器相比,History Cell引入了74%的面积开销和106%的功率开销。扩展具有校正功能的现有dmr架构的面积和功率开销分别约为24%和28%。
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引用次数: 2
Resilient random modulo cache memories for probabilistically-analyzable real-time systems 用于概率分析实时系统的弹性随机模缓存存储器
David Trilla, Carles Hernández, J. Abella, F. Cazorla
Fault tolerance has often been assessed separately in safety-related real-time systems, which may lead to inefficient solutions. Recently, Measurement-Based Probabilistic Timing Analysis (MBPTA) has been proposed to estimate Worst-Case Execution Time (WCET) on high performance hardware. The intrinsic probabilistic nature of MBPTA-commpliant hardware matches perfectly with the random nature of hardware faults. Joint WCET analysis and reliability assessment has been done so far for some MBPTA-compliant designs, but not for the most promising cache design: random modulo. In this paper we perform, for the first time, an assessment of the aging-robustness of random modulo and propose new implementations preserving the key properties of random modulo, a.k.a. low critical path impact, low miss rates and MBPTA compliance, while enhancing reliability in front of aging by achieving a better - yet random - activity distribution across cache sets.
在与安全相关的实时系统中,容错性通常是单独评估的,这可能导致低效的解决方案。近年来,基于测量的概率时序分析(MBPTA)被提出用于估计高性能硬件上的最坏情况执行时间(WCET)。mbpta硬件的固有概率特性与硬件故障的随机特性完美匹配。到目前为止,已经对一些符合mbpta的设计进行了联合WCET分析和可靠性评估,但没有对最有前途的缓存设计:随机模。在本文中,我们首次对随机模的老化鲁棒性进行了评估,并提出了新的实现方法,保留了随机模的关键特性,即低关键路径影响,低缺失率和MBPTA合规性,同时通过实现更好的随机活动分布来提高老化前的可靠性。
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引用次数: 4
Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks IEEE 1687网络故障诊断的自动生成激励
R. Cantoro, Mehrdad Montazeri, M. Reorda, Farrokh Ghani Zadegan, E. Larsson
The IEEE 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, debug, calibration, etc.), by the use of configurable modules acting as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. Since the resulting networks could inevitably be affected by defects which may prevent their correct usage, solutions allowing not only to test against these defects, but also to diagnose them (i.e., to identify the location of possible faults) are of uttermost importance. This paper proposes a method to automatically generate suitable test stimuli: by applying them and observing the output of the network one can not only detect possible faults, but also identify the fault responsible for the misbehavior. Experimental results gathered on a set of benchmark networks with a prototypical tool implementing the proposed techniques show the feasibility and provide a first idea about the length of the required input stimuli.
IEEE 1687标准描述了可重构结构,通过使用可配置模块作为可控开关,允许灵活地访问设备内现有的仪器(例如,支持测试,调试,校准等)。越来越多地采用该标准需要可用的算法和工具来自动化其使用。由于最终的网络不可避免地会受到缺陷的影响,这可能会阻止它们的正确使用,因此解决方案不仅要允许对这些缺陷进行测试,而且还要允许对它们进行诊断(即,确定可能的故障的位置),这是极其重要的。本文提出了一种自动生成合适的测试刺激的方法:通过应用这些刺激并观察网络的输出,不仅可以检测到可能的故障,还可以识别导致异常行为的故障。使用原型工具在一组基准网络上收集的实验结果显示了可行性,并提供了所需输入刺激长度的初步想法。
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引用次数: 12
An efficient LDPC encoder architecture for space applications 用于空间应用的高效LDPC编码器架构
D. Theodoropoulos, N. Kranitis, A. Paschalis
Quasi-Cyclic Low-Density Parity-Check Codes (QC-LDPC) have been recently adopted by the Consultative Committee for Space Data Systems (CCSDS) as recommended standard for channel coding in near-earth (C2) and deep-space (AR4JA) communications. Existing QC-LDPC encoder architectures proposed in the literature so far, are optimized for other standards (e.g. DVB-S2, IEEE 802.11e), but they are not suitable for efficient implementations for the specific CCSDS codes. In this paper, we introduce for the first time a novel encoder architecture, suitable for these codes. The architecture is a parallel implementation based on a series of recursive convolutional encoders and it leverages the inherent parallelism of generator's matrix QC structure to boost throughput performance. Furthermore, the generic definition of key encoder's parameters provides increased flexibility in terms of latency, FPGA resources and speed. In the special case of C2 code for near-earth communications, a novel architecture is introduced to efficiently handle the challenges arising from the generator's matrix circulant size (511 bits), which is not a power of 2. The proposed encoders operate on a continuous uninterrupted stream of input data and implement all the functions specified by CCSDS data-link layer protocols (i.e. framing, synchronization and randomization). The efficiency of the introduced architecture is demonstrated on a Xilinx XUPV5 development board, achieving multi-Gbps throughput and a significant speed-up when compared with existing approaches.
准循环低密度奇偶校验码(QC-LDPC)最近被空间数据系统咨询委员会(CCSDS)采纳为近地(C2)和深空(AR4JA)通信信道编码的推荐标准。到目前为止,文献中提出的现有QC-LDPC编码器架构针对其他标准(例如DVB-S2, IEEE 802.11e)进行了优化,但它们不适合针对特定的CCSDS代码进行有效实现。在本文中,我们首次介绍了一种适用于这些编码的新型编码器结构。该架构是基于一系列递归卷积编码器的并行实现,并利用生成器矩阵QC结构固有的并行性来提高吞吐量性能。此外,密钥编码器参数的通用定义在延迟、FPGA资源和速度方面提供了更大的灵活性。在近地通信C2码的特殊情况下,引入了一种新的架构来有效地处理发电机矩阵循环大小(511位)所带来的挑战,该矩阵循环大小不是2的幂次。所提出的编码器在连续不间断的输入数据流上运行,并实现CCSDS数据链路层协议规定的所有功能(即分帧,同步和随机化)。在Xilinx XUPV5开发板上演示了所介绍架构的效率,与现有方法相比,实现了数gbps的吞吐量和显着的加速。
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引用次数: 12
Hardware Trojans classification for gate-level netlists based on machine learning 基于机器学习的门级网络列表硬件木马分类
Kento Hasegawa, Masaru Oya, M. Yanagisawa, N. Togawa
Recently, we face a serious risk that malicious third-party vendors can very easily insert hardware Trojans into their IC products but it is very difficult to analyze huge and complex ICs. In this paper, we propose a hardware-Trojan classification method to identify hardware-Trojan infected nets (or Trojan nets) using a support vector machine (SVM). Firstly, we extract the five hardware-Trojan features in each net in a netlist. Secondly, since we cannot effectively give the simple and fixed threshold values to them to detect hardware Trojans, we represent them to be a five-dimensional vector and learn them by using SVM. Finally, we can successfully classify a set of all the nets in an unknown netlist into Trojan ones and normal ones based on the learned SVM classifier. We have applied our SVM-based hardware-Trojan classification method to Trust-HUB benchmarks and the results demonstrate that our method can much increase the true positive rate compared to the existing state-of-the-art results in most of the cases. In some cases, our method can achieve the true positive rate of 100%, which shows that all the Trojan nets in a netlist are completely detected by our method.
最近,我们面临着一个严重的风险,恶意的第三方供应商可以很容易地在他们的IC产品中插入硬件木马,但分析大型和复杂的IC非常困难。本文提出了一种基于支持向量机(SVM)的硬件木马分类方法来识别硬件木马感染网络(或特洛伊网络)。首先,我们在一个网表中提取每个网中的五个硬件木马特征。其次,由于我们无法有效地给出简单固定的阈值来检测硬件木马,我们将它们表示为一个五维向量,并使用SVM进行学习。最后,基于学习到的SVM分类器,我们可以成功地将未知网络列表中的所有网络分类为特洛伊网络和正常网络。我们将基于svm的硬件木马分类方法应用于Trust-HUB基准测试,结果表明,在大多数情况下,与现有的最先进的结果相比,我们的方法可以大大提高真阳性率。在某些情况下,我们的方法可以达到100%的真阳性率,这表明我们的方法可以完全检测到网表中所有的特洛伊网络。
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引用次数: 85
On the robustness of DCT-based compression algorithms for space applications 基于dct的空间压缩算法的鲁棒性研究
Serhiy Avramenko, M. Reorda, M. Violante, Görschwin Fey, Jan-Gerd Mess, R. Schmidt
High compression ratio is crucial to cope with the large amounts of data produced by telemetry sensors and the limited transmission bandwidth typical of space applications. A new generation of telemetry units is under development, based on Commercial Off-The-Shelf (COTS) components that may be subject to misbehaviors due to radiation-induced soft errors. The purpose of this paper is to study the impact of soft errors on different configurations of a discrete cosine transform (DCT)-based compression algorithm. This work's main contribution lies in providing some design guidelines.
高压缩比对于处理遥测传感器产生的大量数据和空间应用典型的有限传输带宽至关重要。基于商用现货(COTS)组件的新一代遥测单元正在开发中,这些组件可能由于辐射引起的软误差而导致行为不当。本文的目的是研究软误差对基于离散余弦变换(DCT)的压缩算法的不同配置的影响。这项工作的主要贡献在于提供了一些设计指南。
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引用次数: 4
期刊
2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)
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