Research on improvement of reference voltage shift of wire-bound products

Abstract

The paper should start with a brief abstract of approximately 100 words summarizing the main goals, developments, and achievements of the work. Consider that the abstract may be included in abstract search databases. Think of what requirements the abstract should fulfill in view of this perspective, taking into account the fact that the main text part will not be accessible to the searching person. For wafer-level package and flip chip package, bump connection reliability may be caused by overall package stress. Therefore, it is well known in the industry that PI will be used as the buffer layer, and low-stress assembly materials include substrate materials will be used to improve the yield and reliability of subsequent package and application due to high stress. For traditional WB products, considering that the chip size is smaller and most of them are wire bond products without soft bump, they are less sensitive to stress, also due the PI cost is relative high, so few researches will focus on the stress improvement of WB products. However, our research shows that some stress-sensitive WB products may cause high yield loss of reference Voltage(Vr) shift due to high stress. The Vr yield loss exceeds 10% or even 20%. In this paper, DOE of the stress effect of PI materials, different EMC materials and package structures on WB products is studied to help select the best production process and material parameters to obtain the highest yield for our proudcts.