Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282429
W. Lau
Previously, the author suggested that the atomic layer deposition (ALD) of an amorphous high-k dielectric thin film has a surface smoothing effect on a rough surface. In this paper, the author points out that for ALD high-k dielectric materials which tend to be polycrystalline, the situation is different. When the film is very thin, it can be amorphous with a surface smoothing effect; when the film is thicker than a critical thickness, it can be polycrystalline with a surface roughening effect. An asymmetry in interfacial roughness will lead to an asymmetry in the top and bottom Schottky barrier heights, resulting in I-V polarity asymmetry. The significance of this theory on the leakage current mechanism of ZAZ MIM capacitors used in DRAM technology will be explained.
{"title":"Surface Smoothing and Roughening Effects of High-K Dielectric Materials Deposited by Atomic Layer Deposition and Their Significance for MIM Capacitors Used in Dram Technology Part II","authors":"W. Lau","doi":"10.1109/CSTIC49141.2020.9282429","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282429","url":null,"abstract":"Previously, the author suggested that the atomic layer deposition (ALD) of an amorphous high-k dielectric thin film has a surface smoothing effect on a rough surface. In this paper, the author points out that for ALD high-k dielectric materials which tend to be polycrystalline, the situation is different. When the film is very thin, it can be amorphous with a surface smoothing effect; when the film is thicker than a critical thickness, it can be polycrystalline with a surface roughening effect. An asymmetry in interfacial roughness will lead to an asymmetry in the top and bottom Schottky barrier heights, resulting in I-V polarity asymmetry. The significance of this theory on the leakage current mechanism of ZAZ MIM capacitors used in DRAM technology will be explained.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72766189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282518
Hua Chen, Pan Zhao, Jiahao Liu, Yusen Su, Tuo Zheng, Hao Ni, Liang He
The leakage currents of 4H-SiC MOSFET were measured at different gate voltages and temperatures, which revealed the critical condition of differentiating FN tunneling current from Ohmic current and FP emission. By assuming that the critical conditions indicated the applicable conditions of E model and l/E model, a unified time-dependent-dielectric-breakdown (TDDB) model was proposed, which predicted a TDDB lifetime longer than that of E model, and lower than that of l/E model. Keywords-TDDB lifetime model; FN tunneling; Ohmic current; FP emission; 4H-SiC MOSFETs; E model; l/Emodel
{"title":"A Unified 4H-SIC Mosfets TDDB Lifetime Model Based on Leakage Current Mechanism","authors":"Hua Chen, Pan Zhao, Jiahao Liu, Yusen Su, Tuo Zheng, Hao Ni, Liang He","doi":"10.1109/CSTIC49141.2020.9282518","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282518","url":null,"abstract":"The leakage currents of 4H-SiC MOSFET were measured at different gate voltages and temperatures, which revealed the critical condition of differentiating FN tunneling current from Ohmic current and FP emission. By assuming that the critical conditions indicated the applicable conditions of E model and l/E model, a unified time-dependent-dielectric-breakdown (TDDB) model was proposed, which predicted a TDDB lifetime longer than that of E model, and lower than that of l/E model. Keywords-TDDB lifetime model; FN tunneling; Ohmic current; FP emission; 4H-SiC MOSFETs; E model; l/Emodel","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"36 1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75678017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282458
C. Muller, Henry Yu, D. Lu
The Yield Enhancement Chapter of the International Roadmap for Devices and Systems (IRDS), and more specifically, the focus topics of Wafer Environment Contaminant Control and Surface Environment Contaminant Control, are responsible for identifying airborne molecular contamination (AMC) and setting guideline limits in all areas of semiconductor processing. Today AMC control is required in FEOL and BEOL operations and this control may be achieved fab-wide or at certain critical processes, potentially also at different levels for different processes.
{"title":"From Microns to Nanometers: The IRDS and AMC Control","authors":"C. Muller, Henry Yu, D. Lu","doi":"10.1109/CSTIC49141.2020.9282458","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282458","url":null,"abstract":"The Yield Enhancement Chapter of the International Roadmap for Devices and Systems (IRDS), and more specifically, the focus topics of Wafer Environment Contaminant Control and Surface Environment Contaminant Control, are responsible for identifying airborne molecular contamination (AMC) and setting guideline limits in all areas of semiconductor processing. Today AMC control is required in FEOL and BEOL operations and this control may be achieved fab-wide or at certain critical processes, potentially also at different levels for different processes.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"220 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77418490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to their low-cost in manufacturing, size-tunable spectral sensitivity, and flexible substrate compatibility, lead sulphide colloidal quantum dots (PbS CQDs) are increasingly regarded as promising active material candidates for next-generation NIR photodetectors. In this study, the effective passivation on the surface of PbS CQDs with perovskites is demonstrated, and the perovskite-treated PbS CQDs show improved ambient stability and reduced agglomeration. The PbS CQDs photodiode detectors are self-powered and exhibit a high on/off ratio up to 3×104 along with a large photocurrent density of 2 mA cm−2. Meanwhile, the photoconductor structured photodetectors based on the same materials, displays a responsivity of 0.48 A W−1 and excellent long-term stability in ambient atmosphere.
由于其制造成本低，光谱灵敏度可调，以及柔性衬底兼容性，硫化铅胶体量子点(PbS CQDs)越来越被认为是下一代近红外光电探测器的有前途的活性材料候选者。在本研究中，证明了钙钛矿对PbS CQDs表面的有效钝化，钙钛矿处理的PbS CQDs表现出更好的环境稳定性和减少团聚。PbS CQDs光电二极管探测器是自供电的，具有高达3×104的高开/关比以及2 mA cm−2的大光电流密度。与此同时，基于相同材料的光导体结构光电探测器的响应率为0.48 a W−1，并且在环境大气中具有良好的长期稳定性。
{"title":"Ambient-Stable and High On/Off Ratio Near-Infrared Photodetector Based on Perovskite-Treated PbS Colloidal Quantum Dots","authors":"Qingqing Wu, Yajie Yan, Ziqi Liang, ShaoJian Hu, Jianjun Zhu, Shoumian Chen","doi":"10.1109/CSTIC49141.2020.9282505","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282505","url":null,"abstract":"Due to their low-cost in manufacturing, size-tunable spectral sensitivity, and flexible substrate compatibility, lead sulphide colloidal quantum dots (PbS CQDs) are increasingly regarded as promising active material candidates for next-generation NIR photodetectors. In this study, the effective passivation on the surface of PbS CQDs with perovskites is demonstrated, and the perovskite-treated PbS CQDs show improved ambient stability and reduced agglomeration. The PbS CQDs photodiode detectors are self-powered and exhibit a high on/off ratio up to 3×104 along with a large photocurrent density of 2 mA cm−2. Meanwhile, the photoconductor structured photodetectors based on the same materials, displays a responsivity of 0.48 A W−1 and excellent long-term stability in ambient atmosphere.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"13 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81600634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282512
Kaixuan Du, Ziyuan Xu, Xiulong Wu, Libo Yang, Hao Zhang, Zhixuan Wang, Le Ye
This paper proposed a nano-watt voltage reference circuit was implemented in a 0.18um CMOS process with trim techniques. In order to reduce power consumption, a MOS-Only Voltage Reference is presented, which is based on the threshold voltage, However, the deviation of Vref because of process variation is large. We use the difference of Vth instead of Vth to improve the stability of output voltage at different process corner. The simulation results show that under 27°C and 0.5V supply voltage, the output reference voltage is 236mV, the temperature coefficient is 30.8 ppm/°C over temperature range of 125°C (-40°C to 85°C) and only consume 5.5nW at 0.5V supply voltage.
{"title":"A 5.5nW Voltage Reference Circuit","authors":"Kaixuan Du, Ziyuan Xu, Xiulong Wu, Libo Yang, Hao Zhang, Zhixuan Wang, Le Ye","doi":"10.1109/CSTIC49141.2020.9282512","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282512","url":null,"abstract":"This paper proposed a nano-watt voltage reference circuit was implemented in a 0.18um CMOS process with trim techniques. In order to reduce power consumption, a MOS-Only Voltage Reference is presented, which is based on the threshold voltage, However, the deviation of Vref because of process variation is large. We use the difference of Vth instead of Vth to improve the stability of output voltage at different process corner. The simulation results show that under 27°C and 0.5V supply voltage, the output reference voltage is 236mV, the temperature coefficient is 30.8 ppm/°C over temperature range of 125°C (-40°C to 85°C) and only consume 5.5nW at 0.5V supply voltage.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86017260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282455
Yang Chen, Na Mei, Tuobei Sun
The paper should start with a brief abstract of approximately 100 words summarizing the main goals, developments, and achievements of the work. Consider that the abstract may be included in abstract search databases. Think of what requirements the abstract should fulfill in view of this perspective, taking into account the fact that the main text part will not be accessible to the searching person. For wafer-level package and flip chip package, bump connection reliability may be caused by overall package stress. Therefore, it is well known in the industry that PI will be used as the buffer layer, and low-stress assembly materials include substrate materials will be used to improve the yield and reliability of subsequent package and application due to high stress. For traditional WB products, considering that the chip size is smaller and most of them are wire bond products without soft bump, they are less sensitive to stress, also due the PI cost is relative high, so few researches will focus on the stress improvement of WB products. However, our research shows that some stress-sensitive WB products may cause high yield loss of reference Voltage(Vr) shift due to high stress. The Vr yield loss exceeds 10% or even 20%. In this paper, DOE of the stress effect of PI materials, different EMC materials and package structures on WB products is studied to help select the best production process and material parameters to obtain the highest yield for our proudcts.
{"title":"Research on improvement of reference voltage shift of wire-bound products","authors":"Yang Chen, Na Mei, Tuobei Sun","doi":"10.1109/CSTIC49141.2020.9282455","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282455","url":null,"abstract":"The paper should start with a brief abstract of approximately 100 words summarizing the main goals, developments, and achievements of the work. Consider that the abstract may be included in abstract search databases. Think of what requirements the abstract should fulfill in view of this perspective, taking into account the fact that the main text part will not be accessible to the searching person. For wafer-level package and flip chip package, bump connection reliability may be caused by overall package stress. Therefore, it is well known in the industry that PI will be used as the buffer layer, and low-stress assembly materials include substrate materials will be used to improve the yield and reliability of subsequent package and application due to high stress. For traditional WB products, considering that the chip size is smaller and most of them are wire bond products without soft bump, they are less sensitive to stress, also due the PI cost is relative high, so few researches will focus on the stress improvement of WB products. However, our research shows that some stress-sensitive WB products may cause high yield loss of reference Voltage(Vr) shift due to high stress. The Vr yield loss exceeds 10% or even 20%. In this paper, DOE of the stress effect of PI materials, different EMC materials and package structures on WB products is studied to help select the best production process and material parameters to obtain the highest yield for our proudcts.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"10 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77094075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282605
M. Duan, J. F. Zhang, Z. Ji, W. Zhang
Early works on device ageing often focus on one source, while devices in a circuit suffer degradation from different sources. There are only limited information on the impact of ageing from one source on ageing from a different source. This work researches into the interaction of ageing induced by Hot Carriers with that by Positive Bias Temperature Instability (PBTI). It will be shown that one can slow down the other and the ageing can be substantially overestimated without considering their interaction. Although a PBTI after Hot Carrier Ageing (HCA) will increase the degradation, a HCA following a PBTI can result in a reduction in ageing for long channel devices. The defect responsible for their interaction will be explored.
{"title":"Towards Understanding Interaction Between Hot Carrier Ageing and PBTI","authors":"M. Duan, J. F. Zhang, Z. Ji, W. Zhang","doi":"10.1109/CSTIC49141.2020.9282605","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282605","url":null,"abstract":"Early works on device ageing often focus on one source, while devices in a circuit suffer degradation from different sources. There are only limited information on the impact of ageing from one source on ageing from a different source. This work researches into the interaction of ageing induced by Hot Carriers with that by Positive Bias Temperature Instability (PBTI). It will be shown that one can slow down the other and the ageing can be substantially overestimated without considering their interaction. Although a PBTI after Hot Carrier Ageing (HCA) will increase the degradation, a HCA following a PBTI can result in a reduction in ageing for long channel devices. The defect responsible for their interaction will be explored.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"95 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73598223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a Conditional Generative Adversarial Network (CGAN) [1] is demonstrated based on the Resistive Random Access Memory (RRAM). During training, the read noise of RRAM is utilized as a random bias source to enrich the diversity of the generator in CGAN. Further, we evaluate the impact of both read noise (RRAM as weight storage cell) and the resolution of the AD/DA circuit on the performance of CGAN through a comprehensive simulation.
{"title":"Impact of Circuit Limit and Device Noise on RRAM Based Conditional Generative Adversarial Network","authors":"Shengyu Bao, Zongwei Wang, Tianyi Liu, Daqin Chen, Yimao Cai, Ru Huang","doi":"10.1109/CSTIC49141.2020.9282546","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282546","url":null,"abstract":"In this work, a Conditional Generative Adversarial Network (CGAN) [1] is demonstrated based on the Resistive Random Access Memory (RRAM). During training, the read noise of RRAM is utilized as a random bias source to enrich the diversity of the generator in CGAN. Further, we evaluate the impact of both read noise (RRAM as weight storage cell) and the resolution of the AD/DA circuit on the performance of CGAN through a comprehensive simulation.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85806568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282396
Zhenghong Liu, Liqun Dong, R. Qi, Shugang Dai, Guanqun Huang, Haoyu Chen, Chris Shao
The improvement of Gate induced drain leakage (GIDL) is studied in 2T SONOS (silicon-oxide-nitride-oxide-silicon) nonvolatile memory. High GIDL current from the select gate (SG) introduce inhibit disturb to the neighbor SONOS gate. It is found that these leakage bits impact the overall yield and reliability. In this paper, the variation trend of GIDL leakage with LDD dopant dose, energy and tilt is investigated in detail Results show that GIDL leakage is effectively decreased through increasing tilt and energy or decreasing the dose amount of select gate LDD IMP step. In addition, GIDL leakage also decreased by changing SG LDD dopant step from post poly re-oxidation to post spacer1 etch which increased the space of SG gate to drain. The proposed condition improves GIDL current by one order of magnitude; yield and Vt window are also greatly increased.
{"title":"Study of GIDL Improvement for 2T-SONOS Flash","authors":"Zhenghong Liu, Liqun Dong, R. Qi, Shugang Dai, Guanqun Huang, Haoyu Chen, Chris Shao","doi":"10.1109/CSTIC49141.2020.9282396","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282396","url":null,"abstract":"The improvement of Gate induced drain leakage (GIDL) is studied in 2T SONOS (silicon-oxide-nitride-oxide-silicon) nonvolatile memory. High GIDL current from the select gate (SG) introduce inhibit disturb to the neighbor SONOS gate. It is found that these leakage bits impact the overall yield and reliability. In this paper, the variation trend of GIDL leakage with LDD dopant dose, energy and tilt is investigated in detail Results show that GIDL leakage is effectively decreased through increasing tilt and energy or decreasing the dose amount of select gate LDD IMP step. In addition, GIDL leakage also decreased by changing SG LDD dopant step from post poly re-oxidation to post spacer1 etch which increased the space of SG gate to drain. The proposed condition improves GIDL current by one order of magnitude; yield and Vt window are also greatly increased.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"43 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82532375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282562
J. Broz, Bret A. Humphrey
Accurate testing of advanced devices using sockets is the primary method of assuring that the final assembled devices meet performance and reliability specifications. During any device test operation, contact is made with the device in a socket and, consequently, contamination from the package accumulates into the socket and onto the contactor surfaces. To maintain high yields during test operations, the sockets and contactors must be regularly cleaned. Modern production handlers are equipped for auto-contactor cleaning (ACC) functions to reduce downtime and maintain high throughput. In this paper, implementation of cleaning units used for in-situ cleaning execution are presented; and production test results are presented with an emphasis on the overall performance for the long-term cleaning effects and reduced total test time. A successful customer implementation shows the benefits of this approach within a high-volume testing environment.
{"title":"Yield Improvement and Cost of Test Reduction Via Automated Socket Cleaning","authors":"J. Broz, Bret A. Humphrey","doi":"10.1109/CSTIC49141.2020.9282562","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282562","url":null,"abstract":"Accurate testing of advanced devices using sockets is the primary method of assuring that the final assembled devices meet performance and reliability specifications. During any device test operation, contact is made with the device in a socket and, consequently, contamination from the package accumulates into the socket and onto the contactor surfaces. To maintain high yields during test operations, the sockets and contactors must be regularly cleaned. Modern production handlers are equipped for auto-contactor cleaning (ACC) functions to reduce downtime and maintain high throughput. In this paper, implementation of cleaning units used for in-situ cleaning execution are presented; and production test results are presented with an emphasis on the overall performance for the long-term cleaning effects and reduced total test time. A successful customer implementation shows the benefits of this approach within a high-volume testing environment.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"257 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76187050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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