{"title":"First run S-DMB MMIC low noise amplifier","authors":"Y. Jato, C. Perez, A. Herrera, L. Diego","doi":"10.1109/CDE.2013.6481393","DOIUrl":null,"url":null,"abstract":"This paper reports on the simulation steps needed to design a GaAs MMIC LNA for S-DMB on-board satellite applications in only one fabrication iteration, which achieves a noise figure <; 1.3 dB and gain> 28 dB for applications from 1.95 to 2.3 GHz. In addition, the amplifier obtains a high linearity with an OIP3 of 20.7 dBm and PldB of 6 dBm over a 1.95-2.3 GHz bandwidth. Availability of accurate library simulation models and the use of ADS co-simulation scheme permit us reducing design time and more importantly obtaining a first run working chip.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"144 1","pages":"265-268"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Spanish Conference on Electron Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CDE.2013.6481393","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
This paper reports on the simulation steps needed to design a GaAs MMIC LNA for S-DMB on-board satellite applications in only one fabrication iteration, which achieves a noise figure <; 1.3 dB and gain> 28 dB for applications from 1.95 to 2.3 GHz. In addition, the amplifier obtains a high linearity with an OIP3 of 20.7 dBm and PldB of 6 dBm over a 1.95-2.3 GHz bandwidth. Availability of accurate library simulation models and the use of ADS co-simulation scheme permit us reducing design time and more importantly obtaining a first run working chip.
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