A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF

Abstract

This paper presents a highly power-efficient instrumentation amplifier. It adopts an inverter stacking amplifier (ISA) based 1st-stage that realizes 4x current reuse, thereby greatly reducing the supply current. To boost the power efficiency and enable its robust operation under 0.6V supply, the tail current sources are removed. A high CMRR of 84dB is maintained by combining chopping, closed-loop biasing, and inherent high impedance degeneration. A 3-stage topology with a class-AB last-stage realizes high loop gain and power-efficient dominant-pole compensation. A prototype tail-less ISA in 180nm achieves 1.38uV rms input referred noise (IRN) within 8-kHz BW, while consuming only 2.7uW. This leads to a power efficiency factor (PEF) of 0.96. To authors’ best knowledge, it is the best reported PEF to date.