Pub Date : 2019-06-14DOI: 10.23919/VLSIC.2019.8778050
Chenghan Li, Luca Longinotti, Federico Corradi, T. Delbrück
This paper reports a 132 by 104 dynamic vision sensor (DVS) with $10 mu mathrm{m}$ pixel in a 65nm logic process and a synchronous address-event representation (SAER) readout capable of 180Meps throughput. The SAER architecture allows adjustable event frame rate control and supports pre-readout pixel-parallel noise and spatial redundancy suppression. The chip consumes $250 mu mathrm{W}$ with 100keps running at 1k event frames per second (efps), 3-5 times more power efficient than the prior art using normalized power metrics. The chip is aimed for low power IoT and real-time high-speed smart vision applications.
本文报道了一个132 × 104动态视觉传感器(DVS)，在65nm逻辑工艺中具有$10 mu maththrm {m}$像素，具有能够实现180Meps吞吐量的同步地址事件表示(SAER)读出。SAER架构允许可调的事件帧率控制，并支持预读出像素并行噪声和空间冗余抑制。该芯片以每秒1k事件帧(efps)的速度运行100次，功耗为250美元mu mathm {W}$，使用标准化功耗指标比现有技术节能3-5倍。该芯片旨在实现低功耗物联网和实时高速智能视觉应用。
{"title":"A 132 by 104 10μm-Pixel 250μW 1kefps Dynamic Vision Sensor with Pixel-Parallel Noise and Spatial Redundancy Suppression","authors":"Chenghan Li, Luca Longinotti, Federico Corradi, T. Delbrück","doi":"10.23919/VLSIC.2019.8778050","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778050","url":null,"abstract":"This paper reports a 132 by 104 dynamic vision sensor (DVS) with $10 mu mathrm{m}$ pixel in a 65nm logic process and a synchronous address-event representation (SAER) readout capable of 180Meps throughput. The SAER architecture allows adjustable event frame rate control and supports pre-readout pixel-parallel noise and spatial redundancy suppression. The chip consumes $250 mu mathrm{W}$ with 100keps running at 1k event frames per second (efps), 3-5 times more power efficient than the prior art using normalized power metrics. The chip is aimed for low power IoT and real-time high-speed smart vision applications.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"6 1","pages":"C216-C217"},"PeriodicalIF":0.0,"publicationDate":"2019-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85207125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-12DOI: 10.23919/VLSIC.2019.8778081
Dong-Kyu Kim, Hyunsik Kim
This paper presents a low-dropout (LDO) regulators that can supply up to 0.3A output current with high power supply rejection (PSR). The proposed BGR-recursive LDO design with PSR-boosting feedforward improves the PSR while consuming a low quiescent current of $le 50 mu mathrm {A}$. Among the state-of-the-art LDOs, the proposed chip fabricated in $0.5 mu mathrm {m}$ CMOS achieves the highest PSR of 102-to-80dB in the frequency range from 100Hz to 0.1MHz with a current efficiency of 99.98% and shows the best FoM of 11ps in the transient response performance.
本文提出了一种低差(LDO)稳压器，可以提供高达0.3A的输出电流，具有高电源抑制(PSR)。提出的bgr -递归LDO设计具有PSR增强前馈，提高了PSR，同时消耗了$le 50 mu mathrm {A}$的低静态电流。在最先进的ldo中，该芯片在$0.5 mu mathrm {m}$ CMOS中制造，在100Hz至0.1MHz的频率范围内实现了102至80db的最高PSR，电流效率为99.98% and shows the best FoM of 11ps in the transient response performance.
{"title":"A 300mA BGR-Recursive Low-Dropout Regulator Achieving 102-to-80dB PSR at Frequencies from 100Hz to 0.1MHz with Current Efficiency of 99.98%","authors":"Dong-Kyu Kim, Hyunsik Kim","doi":"10.23919/VLSIC.2019.8778081","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778081","url":null,"abstract":"This paper presents a low-dropout (LDO) regulators that can supply up to 0.3A output current with high power supply rejection (PSR). The proposed BGR-recursive LDO design with PSR-boosting feedforward improves the PSR while consuming a low quiescent current of $le 50 mu mathrm {A}$. Among the state-of-the-art LDOs, the proposed chip fabricated in $0.5 mu mathrm {m}$ CMOS achieves the highest PSR of 102-to-80dB in the frequency range from 100Hz to 0.1MHz with a current efficiency of 99.98% and shows the best FoM of 11ps in the transient response performance.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"1 1","pages":"C132-C133"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75755248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-11DOI: 10.23919/VLSIC.2019.8778096
Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim, S. Ryu
This paper presents a four-channel time-interleaved high-speed current-steering DAC with a proposed two-stage analog multiplexer (MUX). Optimum switching times of the cascaded MUX and the sub-DACs are guaranteed by background clock phase calibration with a proposed maximum-overlap-based phase detector. A 6b 28GS/s prototype DAC fabricated in 40nm CMOS achieves a SFDR of 34.6dB at a Nyquist input and consumes 103mW under dual supply voltages of 1.1V and 1.6V.
{"title":"A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration","authors":"Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim, S. Ryu","doi":"10.23919/VLSIC.2019.8778096","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778096","url":null,"abstract":"This paper presents a four-channel time-interleaved high-speed current-steering DAC with a proposed two-stage analog multiplexer (MUX). Optimum switching times of the cascaded MUX and the sub-DACs are guaranteed by background clock phase calibration with a proposed maximum-overlap-based phase detector. A 6b 28GS/s prototype DAC fabricated in 40nm CMOS achieves a SFDR of 34.6dB at a Nyquist input and consumes 103mW under dual supply voltages of 1.1V and 1.6V.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"37 1","pages":"C138-C139"},"PeriodicalIF":0.0,"publicationDate":"2019-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80399568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-11DOI: 10.23919/VLSIC.2019.8778005
M. Seo, Ye-Dam Kim, Jae-Hyun Chung, S. Ryu
This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.
{"title":"A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC","authors":"M. Seo, Ye-Dam Kim, Jae-Hyun Chung, S. Ryu","doi":"10.23919/VLSIC.2019.8778005","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778005","url":null,"abstract":"This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"11 1","pages":"C72-C73"},"PeriodicalIF":0.0,"publicationDate":"2019-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84314174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIC.2019.8778172
A. Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, J. Fox, K. Gharibdoust, Davide Gorret, A. Gupta, Christopher Hall, A. Hassanin, Klaas L. Hofstra, Brian Holden, A. Hormati, J. Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, S. Raparthy, A. Shokrollahi, David Stauffer, Richard Simpson, A. Stewart, G. Surace, O. Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
A 1.02pJ/b USR link carrying 416.67 Gb/s/mm die edge (500Gb/s aggregated data rate) in 16nm FinFET, while occupying 2.4mm2, is presented. To enable dense routing over conventional package material, a modified correlated NRZ signaling with low sensitivity to ISI, Xtalk, and common-mod noise has been developed. A matched CTLE/slicer topology has been employed to enhance robustness of the receiver over PVT. A very wideband Rx PLL tracks the majority of Tx jitter, resulting in significant power saving by relaxing Tx design constraints.
{"title":"A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET","authors":"A. Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, J. Fox, K. Gharibdoust, Davide Gorret, A. Gupta, Christopher Hall, A. Hassanin, Klaas L. Hofstra, Brian Holden, A. Hormati, J. Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, S. Raparthy, A. Shokrollahi, David Stauffer, Richard Simpson, A. Stewart, G. Surace, O. Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh","doi":"10.23919/VLSIC.2019.8778172","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778172","url":null,"abstract":"A 1.02pJ/b USR link carrying 416.67 Gb/s/mm die edge (500Gb/s aggregated data rate) in 16nm FinFET, while occupying 2.4mm2, is presented. To enable dense routing over conventional package material, a modified correlated NRZ signaling with low sensitivity to ISI, Xtalk, and common-mod noise has been developed. A matched CTLE/slicer topology has been employed to enhance robustness of the receiver over PVT. A very wideband Rx PLL tracks the majority of Tx jitter, resulting in significant power saving by relaxing Tx design constraints.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"33 1","pages":"C92-C93"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78420865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIC.2019.8778082
H. Ko, Soyeong Shin, Chan-Ho Kye, Sangyoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, D. Jeong
This paper presents a data (DQ) receiver for HBM3 with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift. The self-tracking loop achieves low power and small area by utilizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage difference and detects the phase skew from the voltage difference. An offset calibration scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing circuits by taking advantage of the write training of HBM. Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4.8 Gb/s and occupies 0.0056 mm2. The experimental results show that the DQ receiver operates without any performance degradation under ${a}pm 10$% supply variation.
{"title":"A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop","authors":"H. Ko, Soyeong Shin, Chan-Ho Kye, Sangyoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, D. Jeong","doi":"10.23919/VLSIC.2019.8778082","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778082","url":null,"abstract":"This paper presents a data (DQ) receiver for HBM3 with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift. The self-tracking loop achieves low power and small area by utilizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage difference and detects the phase skew from the voltage difference. An offset calibration scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing circuits by taking advantage of the write training of HBM. Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4.8 Gb/s and occupies 0.0056 mm2. The experimental results show that the DQ receiver operates without any performance degradation under ${a}pm 10$% supply variation.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"19 1","pages":"C94-C94"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76953924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIC.2019.8778028
Ruiqi Guo, Yonggang Liu, Shixuan Zheng, Ssu-Yen Wu, P. Ouyang, W. Khwa, Xi Chen, Jia-Jing Chen, Xiudong Li, Leibo Liu, Meng-Fan Chang, Shaojun Wei, S. Yin
This work presents a 65nm CMOS speech recognition processor, named Thinker-IM, which employs 16 computing-in-memory (SRAM-CIM) macros for binarized recurrent neural network (RNN) computation. Its major contributions are: 1) A novel digital-CIM mixed architecture that runs an output-weight dual stationary (OWDS) dataflow, reducing 85.7% memory accessing; 2) Multi-bit XNOR SRAM-CIM macros and corresponding CIM-aware weight adaptation that reduces 9.9% energy consumption in average; 3) Predictive early batch-normalization (BN) and binarization units (PBUs) that reduce at most 28.3% computations in RNN. Measured results show the processing speed of 127.3us/Inference and over 90.2% accuracy, while achieving neural energy efficiency of 5.1pJ/Neuron, which is 2.8 × better than state-of-the-art.
{"title":"A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS","authors":"Ruiqi Guo, Yonggang Liu, Shixuan Zheng, Ssu-Yen Wu, P. Ouyang, W. Khwa, Xi Chen, Jia-Jing Chen, Xiudong Li, Leibo Liu, Meng-Fan Chang, Shaojun Wei, S. Yin","doi":"10.23919/VLSIC.2019.8778028","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778028","url":null,"abstract":"This work presents a 65nm CMOS speech recognition processor, named Thinker-IM, which employs 16 computing-in-memory (SRAM-CIM) macros for binarized recurrent neural network (RNN) computation. Its major contributions are: 1) A novel digital-CIM mixed architecture that runs an output-weight dual stationary (OWDS) dataflow, reducing 85.7% memory accessing; 2) Multi-bit XNOR SRAM-CIM macros and corresponding CIM-aware weight adaptation that reduces 9.9% energy consumption in average; 3) Predictive early batch-normalization (BN) and binarization units (PBUs) that reduce at most 28.3% computations in RNN. Measured results show the processing speed of 127.3us/Inference and over 90.2% accuracy, while achieving neural energy efficiency of 5.1pJ/Neuron, which is 2.8 × better than state-of-the-art.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"72 1","pages":"C120-C121"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78734696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIC.2019.8778039
Yukun Zhu, P. R. Byreddy, K. O. Kenneth, W. Choi
A 426-GHz imaging pixel integrating a transmitter and a coherent receiver using three oscillators for triple-pushing within an area of 380×470μm2 is demonstrated. The radiated TX power is −17.9 dBm and the sensitivity is −89.6 dBm for a 1-kHz noise bandwidth. The sensitivity is the lowest among imaging pixels operating above 0.3 THz. The pixel consumes 52 mW from a 1.3-V VDD. The pixel can be used with a reflector with 47-dB gain to form a camera-like reflection mode image for an object 5 m away.
一个426 ghz成像像素集成了一个发射器和一个相干接收器，使用三个振荡器在380×470μm2区域内进行三推。在噪声带宽为1khz时，发射的TX功率为−17.9 dBm，灵敏度为−89.6 dBm。在工作在0.3太赫兹以上的成像像素中，灵敏度最低。像素从1.3 v VDD消耗52 mW。该像素可以与增益为47db的反射器一起使用，形成5米外物体的类似相机的反射模式图像。
{"title":"426-GHz Imaging Pixel Integrating a Transmitter and a Coherent Receiver with an Area of 380×47μm2 in 65-nm CMOS","authors":"Yukun Zhu, P. R. Byreddy, K. O. Kenneth, W. Choi","doi":"10.23919/VLSIC.2019.8778039","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778039","url":null,"abstract":"A 426-GHz imaging pixel integrating a transmitter and a coherent receiver using three oscillators for triple-pushing within an area of 380×470μm2 is demonstrated. The radiated TX power is −17.9 dBm and the sensitivity is −89.6 dBm for a 1-kHz noise bandwidth. The sensitivity is the lowest among imaging pixels operating above 0.3 THz. The pixel consumes 52 mW from a 1.3-V VDD. The pixel can be used with a reflector with 47-dB gain to form a camera-like reflection mode image for an object 5 m away.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"10 1","pages":"C18-C19"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82849563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIC.2019.8778059
Haosheng Zhang, A. Narayanan, Hans Herdian, Bangan Liu, Yun Wang, A. Shirane, K. Okada
This paper presents an injection-locked PLL that employs RC pulse generator and injection timing calibration to enhance the jitter and reference spur performance. An ultra-low power oscillator is designed to reduce the overall power consumption of the PLL. The chip is fabricated in 65nm CMOS technology, occupying an area of 0.25mm2. The proposed ILPLL achieves 70fsrms integrated jitter and -66dBc reference spur, while consuming 0.2mW, which translates into -270dB FoM at 2.4GHz output frequency.
{"title":"0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur","authors":"Haosheng Zhang, A. Narayanan, Hans Herdian, Bangan Liu, Yun Wang, A. Shirane, K. Okada","doi":"10.23919/VLSIC.2019.8778059","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8778059","url":null,"abstract":"This paper presents an injection-locked PLL that employs RC pulse generator and injection timing calibration to enhance the jitter and reference spur performance. An ultra-low power oscillator is designed to reduce the overall power consumption of the PLL. The chip is fabricated in 65nm CMOS technology, occupying an area of 0.25mm2. The proposed ILPLL achieves 70fsrms integrated jitter and -66dBc reference spur, while consuming 0.2mW, which translates into -270dB FoM at 2.4GHz output frequency.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"1 1","pages":"C38-C39"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83360655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIC.2019.8777984
Cheonhoo Jeon, Jahyun Koo, Kyong-Taek Lee, Su-Kyoung Kim, S. Hahn, Byungsub Kim, Hong-June Park, J. Sim
This paper presents a smart contact lens (SCL) controller IC with a high-precision current sensor interface and a dual-mode wireless telemetry, where a single power-oscillator-based circuit with an external loop antenna supports both LSK and RF data transmission. The implemented IC in $0.18 mu m$ CMOS, achieving a dynamic conversion range of 89 dB while dissipating 143 nW, is verified in a glucose-sensing SCL system.
{"title":"A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna","authors":"Cheonhoo Jeon, Jahyun Koo, Kyong-Taek Lee, Su-Kyoung Kim, S. Hahn, Byungsub Kim, Hong-June Park, J. Sim","doi":"10.23919/VLSIC.2019.8777984","DOIUrl":"https://doi.org/10.23919/VLSIC.2019.8777984","url":null,"abstract":"This paper presents a smart contact lens (SCL) controller IC with a high-precision current sensor interface and a dual-mode wireless telemetry, where a single power-oscillator-based circuit with an external loop antenna supports both LSK and RF data transmission. The implemented IC in $0.18 mu m$ CMOS, achieving a dynamic conversion range of 89 dB while dissipating 143 nW, is verified in a glucose-sensing SCL system.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"18 1","pages":"C294-C295"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89436520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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