Chenghan Li, Luca Longinotti, Federico Corradi, T. Delbrück
{"title":"A 132 by 104 10μm-Pixel 250μW 1kefps Dynamic Vision Sensor with Pixel-Parallel Noise and Spatial Redundancy Suppression","authors":"Chenghan Li, Luca Longinotti, Federico Corradi, T. Delbrück","doi":"10.23919/VLSIC.2019.8778050","DOIUrl":null,"url":null,"abstract":"This paper reports a 132 by 104 dynamic vision sensor (DVS) with $10 \\mu \\mathrm{m}$ pixel in a 65nm logic process and a synchronous address-event representation (SAER) readout capable of 180Meps throughput. The SAER architecture allows adjustable event frame rate control and supports pre-readout pixel-parallel noise and spatial redundancy suppression. The chip consumes $250 \\mu \\mathrm{W}$ with 100keps running at 1k event frames per second (efps), 3-5 times more power efficient than the prior art using normalized power metrics. The chip is aimed for low power IoT and real-time high-speed smart vision applications.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"6 1","pages":"C216-C217"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778050","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 30
Abstract
This paper reports a 132 by 104 dynamic vision sensor (DVS) with $10 \mu \mathrm{m}$ pixel in a 65nm logic process and a synchronous address-event representation (SAER) readout capable of 180Meps throughput. The SAER architecture allows adjustable event frame rate control and supports pre-readout pixel-parallel noise and spatial redundancy suppression. The chip consumes $250 \mu \mathrm{W}$ with 100keps running at 1k event frames per second (efps), 3-5 times more power efficient than the prior art using normalized power metrics. The chip is aimed for low power IoT and real-time high-speed smart vision applications.
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