Interconnects for next generation SoC designs

Abstract

As the number of functional IP blocks connected on a die increase, SoC development becomes constrained by the capabilities of the on-chip interconnect that connects these IP blocks together. And as the use of commercial IP increase to encompass 80% or more of a commercial SoCs functionality, innovation and differentiation between competing designs could only be expressed in how the IP is connected, as implemented by the on-chip interconnect. To keep up with the demands of the SoC, the interconnects have also become fairly complex and sophisticated. The desire for satisfying the needs of next generation SoCs, while optimizing the area, processing efficiency and power consumption, is driving innovation in switch designs, routing algorithms, transport mechanisms, Quality of Service and coherency schemes. The problem space is big and perhaps more complex in certain ways than that of data networks. The changing application requirements is also changing how we look at Service Level Agreements (SLAs) within the SoC. The SLAs for next generation Interconnects have to go beyond delay and bandwidth considerations to also include resiliency, fault tolerance, and security. In this talk, I will discuss the challenges in building next generation Interconnects, the innovation taking place to address these challenges and how the SoC interconnects are different from the interconnects in data networks.