1 GHz clock operation of Josephson RAMs

Shuichi Nagasawa, Hideaki Numata, Yoshihito Hashimoto, Shuichi Tahara
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引用次数: 1

Abstract

A Josephson 256 word×16 bit RAM that includes a power circuit has been designed to enable high-frequency clock operation. This RAM consists of a 4×4 matrix array of 256 RAM blocks, impedance matching lines, and input signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned properly at a high clock frequency of 1 GHz with less than 3 mW of power dissipation from an external power source.

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1 GHz时钟操作的约瑟夫森RAMs
包含电源电路的约瑟夫逊256 word×16位RAM设计用于实现高频时钟操作。该RAM由256个RAM块的4×4矩阵阵列、阻抗匹配线和输入信号放大器组成。电源电路,由变压器和约瑟夫森稳压器组成,包括在每个256 RAM块中。测量了256 RAM块的故障位映射,并获得了100%比特收率的完美操作。256 RAM块在1ghz的高时钟频率下正常工作,外部电源的功耗小于3mw。
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