Ion beams, thermal processes and lithographic challenges

Abstract

Among the challenges with which lithographers are currently grappling, the issues of line-edge roughness (LER) and non-linear overlay errors intersect the concerns of ion implantation and thermal process engineers. LER, and the associated metric for contact holes, local critical dimension uniformity (LCDU), must be small to meet the requirements of advanced nodes. Photon shot-noise-induced LER and LCDU diminution, which can benefit from high resist exposure doses, must be balanced with exposure tool throughput requirements for meeting cost targets for Moore's Law. Because very small improvements in LER and LCDU can require substantial increases in resist exposure doses, post-lithographic techniques for reducing LER and LCDU can have sizable salutary impact on overall wafer costs. The impact of LER on circuit performance depends on the spatial frequencies comprising the LER, and the criticality of particular ranges of spatial frequencies may shift as a consequence of transitions to new types of devices. LER can be reduced post-lithographically by using charged particle beams. Non-linear wafer distortions, which can result from thermal processes and the etching of high-stress films, are problematic for overlay control. Correction of non-linear overlay errors requires the use of a large number of alignment sites and overlay measurements, again resulting in a trade-off between process control and wafer cost. The impact of these distortions on overlay can be predicted quantitatively by measurements of out-of-plane wafer warp. Such measurements can be used to develop processes with intrinsically low distortion and for maintaining process control in manufacturing.