A design and fabrication of transmission line for eSiFO in millimeter-wave applications

Shengjuan Zhou, Jian Cai, Qian Wang, Xiuyu Shi, Xuesong Zhang, Changmin Song, Yu Chen
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Abstract

In millimeter-wave devices, Fan-out Wafer Level Package for system integration is a popular trend to meet the requirements of high performance, small dimensions and low cost. Compared to conventional Fan-out Wafer Level Package with molding compound, embedded Silicon Fan-out (eSiFO) Wafer Level Package has become an attractive technology due to low cost, less warpage problem and fine-pitch redistribution layer (RDL) production capability. However, silicon substrate is usually of low resistivity, which limits the application of eSiFO technology in millimeter-wave field. Thus, high efficiency and low loss transmission line has become an important topic in eSiFO. In this paper, a design of coplanar waveguide (CPW) with shield line for eSiFO in millimeter-wave applications is proposed. Electrical modeling of transmission line structure was carried out by HFSS. The CPW with and without shield line were fabricated compatible with semiconductor processes. Measurement and test results shows the shield line can provide good impedance matching, suppress undesirable substrate loss, as well as decrease crosstalk from adjacent lines.
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毫米波eSiFO传输线的设计与制作
在毫米波器件中,用于系统集成的扇出晶圆级封装是满足高性能、小尺寸和低成本要求的一种流行趋势。与传统的采用成型化合物的扇出晶圆级封装相比,嵌入式硅扇出(eSiFO)晶圆级封装由于其低成本、较少翘曲问题和细间距再分布层(RDL)生产能力而成为一种有吸引力的技术。然而,硅衬底通常具有低电阻率,这限制了eSiFO技术在毫米波领域的应用。因此,高效、低损耗传输线已成为eSiFO中的重要课题。本文提出了一种毫米波eSiFO用带屏蔽线的共面波导设计方案。利用HFSS软件对输电线路结构进行电气建模。采用兼容的半导体工艺制备了带屏蔽线和不带屏蔽线的CPW。测量和测试结果表明,屏蔽线可以提供良好的阻抗匹配,抑制衬底损耗,减少相邻线路的串扰。
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