Power efficient Vlsi architecture using Sps technique

Abstract

Using spurious power suppression technique (SPST) in VLSI will reduce the power consumption of the system significantly. Here we are going to implement this design in Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter architecture. When we are using this technique in this multipliers the no of partial products generated will be reduced to half which reduces the computation. Then obviously the power consumption is also reduced by this method using the various hardware device.