A Clock-Tuned Discrete-Time Negative Capacitor Implemented Using Analog Samplers

Abstract

The recent introduction of digital non-Foster circuits offers new methods for implementing negative capacitance and inductance, but may require a high-speed high-resolution digital signal processor, analog-to-digital converter, and digital-to-analog converter. Therefore, an alternative discrete-time design approach is presented, where a clock-tuned negative capacitor is implemented using analog samplers. The resulting design requires only two samplers, a differential amplifier, and an operational transconductance amplifier, eliminating the need for a digital signal processor and converters. In addition, it is shown that the negative capacitance can be tuned by the digital clock and is theoretically proportional to the clock period. Experimental results for a prototype demonstrate a tunable capacitance from −2.1 nF to −5.5 nF with |Q| > 2 for signal frequencies below approximately one-tenth of the clock frequency.