An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme

Abstract

An all-digital 7.3Gb/s/pin LPDDR5 PHY is presented. A non-interruptive approximate delay compensation scheme is proposed to enhance tolerance to voltage variation without any memory access black-out. Thus, seamlessly maintained DQ-centering improves access valid-window-margin under supply noise without performance penalty. In addition to that, the proposed scheme enables direct DVFS switching due to the voltage variation tolerance with minimized performance penalty. The LPDDR5 PHY in an 8nm technology demonstrated 6.4Gb/s/pin with 0.31UI at 640mV and 7.3Gb/s/pin with 0.25UI at 790mV, respectively. The voltage variation tolerance is measured up to 70mV without memory access black-out.