Zheyu Liu, Erxiang Ren, Li Luo, Qi Wei, Xing Wu, Xueqing Li, F. Qiao, Xinjun Liu, Huazhong Yang
{"title":"A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications","authors":"Zheyu Liu, Erxiang Ren, Li Luo, Qi Wei, Xing Wu, Xueqing Li, F. Qiao, Xinjun Liu, Huazhong Yang","doi":"10.1109/ISVLSI.2019.00087","DOIUrl":null,"url":null,"abstract":"In the past few years, the demand for intelligence of IoT front-end devices has dramatically increased. However, such devices face challenges of limited on-chip resources and strict power or energy constraints. Recent progress in binarized neural networks has provided promising solutions for front-end processing system to conduct simple detection and classification tasks by making trade-offs between the processing quality and the computation complexity. In this paper, we propose a mixed-signal perception chip, in which an ADC-free 32x32 image sensor and a BNN processing array are directly integrated with a 180nm standard CMOS process. Taking advantage of the ADC-free processing architecture, the whole processing system only consumes 1.8mW power, while providing up to 545.4 GOPS/W energy efficiency. The implementation performance and energy efficiency are comparable with the state-of-the-art designs in much more advanced CMOS technologies. This work provides a promising alternative for low-power IoT intelligent applications.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"42 1","pages":"447-452"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2019.00087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
In the past few years, the demand for intelligence of IoT front-end devices has dramatically increased. However, such devices face challenges of limited on-chip resources and strict power or energy constraints. Recent progress in binarized neural networks has provided promising solutions for front-end processing system to conduct simple detection and classification tasks by making trade-offs between the processing quality and the computation complexity. In this paper, we propose a mixed-signal perception chip, in which an ADC-free 32x32 image sensor and a BNN processing array are directly integrated with a 180nm standard CMOS process. Taking advantage of the ADC-free processing architecture, the whole processing system only consumes 1.8mW power, while providing up to 545.4 GOPS/W energy efficiency. The implementation performance and energy efficiency are comparable with the state-of-the-art designs in much more advanced CMOS technologies. This work provides a promising alternative for low-power IoT intelligent applications.