A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications

C. R. Chappidi, K. Sengupta
{"title":"A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications","authors":"C. R. Chappidi, K. Sengupta","doi":"10.23919/VLSIC.2019.8778095","DOIUrl":null,"url":null,"abstract":"Future mm-Wave transmitter front-ends will need to operate in an electromagnetically complex environment that are resistant to near-field antenna perturbations (VSWR events) while operating across multiple mmWave frequency bands (28/37/39/42 GHz) and with high efficiency and linearity with spectrally efficient modulation. This is particularly difficult since these parameters (bandwidth, linearity, efficiency, and VSWR tolerance) trade off strongly with each other in a power amplifier (PA). In this paper, we present a PA architecture that exploits mutual load pulling through a multi-port network in a nonlinear fashion to achieve VSWR tolerance while demonstrating Doherty-like operation across 26–42 GHz. The PA designed in 65-nm bulk CMOS generates $\\mathrm {{P}_{sat}} \\gt 19$ dBm with $\\mathrm{PAE _{peak}} \\gt 20$% across all bands and achieves up to 3.35x and 4.84x enhancement in PAE at back-off power levels of 6 and 9.6 dB over class-A operation. In addition, the PA demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle and supports 64QAM OFDM modulation with 8 Gbps across 28-40GHz.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"31 1","pages":"C22-C23"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778095","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26

Abstract

Future mm-Wave transmitter front-ends will need to operate in an electromagnetically complex environment that are resistant to near-field antenna perturbations (VSWR events) while operating across multiple mmWave frequency bands (28/37/39/42 GHz) and with high efficiency and linearity with spectrally efficient modulation. This is particularly difficult since these parameters (bandwidth, linearity, efficiency, and VSWR tolerance) trade off strongly with each other in a power amplifier (PA). In this paper, we present a PA architecture that exploits mutual load pulling through a multi-port network in a nonlinear fashion to achieve VSWR tolerance while demonstrating Doherty-like operation across 26–42 GHz. The PA designed in 65-nm bulk CMOS generates $\mathrm {{P}_{sat}} \gt 19$ dBm with $\mathrm{PAE _{peak}} \gt 20$% across all bands and achieves up to 3.35x and 4.84x enhancement in PAE at back-off power levels of 6 and 9.6 dB over class-A operation. In addition, the PA demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle and supports 64QAM OFDM modulation with 8 Gbps across 28-40GHz.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
一种适用于5G应用的26-42 GHz宽带、高效回退和容限驻波CMOS功率放大器架构
未来的毫米波发射机前端将需要在电磁复杂的环境中工作,在多个毫米波频段(28/37/39/42 GHz)上工作时,能够抵抗近场天线扰动(VSWR事件),并具有高效和线性的频谱高效调制。这是特别困难的,因为这些参数(带宽、线性度、效率和VSWR容差)在功率放大器(PA)中相互强烈权衡。在本文中,我们提出了一种PA架构,该架构以非线性方式利用多端口网络的相互负载牵引来实现VSWR容限,同时演示了26-42 GHz的Doherty-like操作。采用65nm块体CMOS设计的PA在所有频段产生$\ mathm {{P}_{sat}} \ gt19 $ dBm, $\ mathm {pae_ {peak}} \ gt20 $%,在6和9.6 dB的回调功率水平下,PAE在a类操作上实现高达3.35倍和4.84倍的增强。此外,PA对VSWR事件具有很强的容错性,在VSWR 4:1负载周期内仅发生2 dB的衰减,并支持28-40GHz范围内8gbps的64QAM OFDM调制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A 132 by 104 10μm-Pixel 250μW 1kefps Dynamic Vision Sensor with Pixel-Parallel Noise and Spatial Redundancy Suppression A 300mA BGR-Recursive Low-Dropout Regulator Achieving 102-to-80dB PSR at Frequencies from 100Hz to 0.1MHz with Current Efficiency of 99.98% A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1