M. Dellutri, P. Pulici, D. Guarnaccia, P. Stoppino, G. Vanalli, T. Lessio, F. Vassallo, R. Di Stefano, G. Labriola, A. Tenerello, F. Lo Iacono, G. Campardo
{"title":"1 Gb stacked solution of multilevel NOR flash memory packaged in a LFBGA 8 mm by 10 mm by 1.4 mm of thickness","authors":"M. Dellutri, P. Pulici, D. Guarnaccia, P. Stoppino, G. Vanalli, T. Lessio, F. Vassallo, R. Di Stefano, G. Labriola, A. Tenerello, F. Lo Iacono, G. Campardo","doi":"10.1109/ESIME.2006.1643997","DOIUrl":null,"url":null,"abstract":"The evolution of electronic world is running toward more and more complex devices even looking for a reduction of the overall system dimensions. This improvement is particularly evident in the wireless applications where portable devices are becoming the key products. Many different applications have been inserted in the last years to satisfy all the increasing final user requirements, without affecting the final device dimensions. This important goal was possible due to many technical achievements in term of integration, the stacked package solutions being the most relevant among them. This assembly technology allows putting more dice one upon the other in a unique package so exploiting its z-dimension. This work aims to describe a multi-memory stacked device of 1 Gb size of the NOR flash memory composed by a four 256Mb dice stacked structure. This solution allows increasing the memory size maintaining the electrical performances of the multilevel NOR flash i.e. speed class. The structure is composed by seven dice: four active and three dummy interposers to create the physical space for the wires bonding from die pads to package substrate (Titus et al., 2004). The package is a LFBGA (low fine pitch ball grid array) 8 mm by 10 mm by 1.4 mm with 88 balls (0.8 mm pitch). An embedded circuitry in the die implements the logic to allow the system to be managed as a monolithic 1 Gb. Moreover, a description of the electrical analysis is reported in order to highlight the electromagnetic interferences between the different dice and the signal integrity of the whole system. Some samples of the device have been assembled in a package without molding in order to make measurements even on the pad of the devices and other critical nodes internal into the package","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"12 1","pages":"1-5"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"微纳电子与智能制造","FirstCategoryId":"1087","ListUrlMain":"https://doi.org/10.1109/ESIME.2006.1643997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The evolution of electronic world is running toward more and more complex devices even looking for a reduction of the overall system dimensions. This improvement is particularly evident in the wireless applications where portable devices are becoming the key products. Many different applications have been inserted in the last years to satisfy all the increasing final user requirements, without affecting the final device dimensions. This important goal was possible due to many technical achievements in term of integration, the stacked package solutions being the most relevant among them. This assembly technology allows putting more dice one upon the other in a unique package so exploiting its z-dimension. This work aims to describe a multi-memory stacked device of 1 Gb size of the NOR flash memory composed by a four 256Mb dice stacked structure. This solution allows increasing the memory size maintaining the electrical performances of the multilevel NOR flash i.e. speed class. The structure is composed by seven dice: four active and three dummy interposers to create the physical space for the wires bonding from die pads to package substrate (Titus et al., 2004). The package is a LFBGA (low fine pitch ball grid array) 8 mm by 10 mm by 1.4 mm with 88 balls (0.8 mm pitch). An embedded circuitry in the die implements the logic to allow the system to be managed as a monolithic 1 Gb. Moreover, a description of the electrical analysis is reported in order to highlight the electromagnetic interferences between the different dice and the signal integrity of the whole system. Some samples of the device have been assembled in a package without molding in order to make measurements even on the pad of the devices and other critical nodes internal into the package