Session 14 overview: High-resolution ADCs: Data converter subcommittee

Abstract

This session's high-resolution analog-to-digital converters (ADCs) with 12 to 19b ENOB introduce a number of advanced circuit design techniques to achieve very high performance with low power consumption. While many of the proposed designs use an efficient SAR architecture where possible for moderate resolution, higher performance is consistently enabled by delta-sigma and pipeline architectures. Precision is further enabled by techniques such as hardware re-use, calibration, dynamic element matching, chopping, and correlated double-sampling.