Effect of gate bias on ESD characteristics in NMOS device

Abstract

Oxide trapped charges which were produced in oxide area of MOSFET in the process of using can cause ESD characteristic changed. So the gate forced given bias to Simulate oxide trapped charges. In this paper, TLP test method was used to study the ESD parameters of NMOSFET with various gate biases. It was indicated that the threshold voltage Vt1 and secondary breakdown current It2 first increased and then decreased with the gate voltage increasing, but the maintained Voltage Vsp essentially unchanged.