{"title":"The Role of Simulation in Failure Prediction and Design Optimization in Electronics Packaging","authors":"A. Tay","doi":"10.1109/ESIME.2006.1644060","DOIUrl":null,"url":null,"abstract":"This paper discusses the role of computer simulation in predicting failure and in optimizing design in electronics packaging. The role played by simulation in predicting failure is illustrated by the use of the fracture mechanics approach in predicting delamination in plastic IC packages undergoing solder reflow. The role played by simulation in optimizing design of IC packages is illustrated by a parametric study of the effect of compliance on the reliability of copper column interconnected wafer level packages. Based on this study, a novel interconnect design is proposed where the interconnect compliance varies continuously from a low value at the centre of the chip to a high value at the perimeter of the chip","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"微纳电子与智能制造","FirstCategoryId":"1087","ListUrlMain":"https://doi.org/10.1109/ESIME.2006.1644060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper discusses the role of computer simulation in predicting failure and in optimizing design in electronics packaging. The role played by simulation in predicting failure is illustrated by the use of the fracture mechanics approach in predicting delamination in plastic IC packages undergoing solder reflow. The role played by simulation in optimizing design of IC packages is illustrated by a parametric study of the effect of compliance on the reliability of copper column interconnected wafer level packages. Based on this study, a novel interconnect design is proposed where the interconnect compliance varies continuously from a low value at the centre of the chip to a high value at the perimeter of the chip