Hui Xu, J. Tanabe, Hiroyuki Usui, Soichiro Hosoda, T. Sano, Kazumasa Yamamoto, T. Kodaka, N. Nonogaki, Nau Ozaki, T. Miyamori
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引用次数: 19
Abstract
A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.
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